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aco: setup subdword regclasses for ssa_undef & load_const 

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
This commit is contained in:
Daniel Schürmann 2020-04-07 10:24:36 +01:00 committed by Marge Bot
parent 67b567d0d0
commit 637f45f390
1 changed files with 8 additions and 12 deletions
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20
src/amd/compiler/aco_instruction_selection_setup.cpp
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@ -361,12 +361,10 @@ void init_context(isel_context *ctx, nir_shader *shader)
break;
}
case nir_instr_type_load_const: {
unsigned size = nir_instr_as_load_const(instr)->def.num_components;
if (nir_instr_as_load_const(instr)->def.bit_size == 64)
size *= 2;
else if (nir_instr_as_load_const(instr)->def.bit_size == 1)
size *= lane_mask_size;
allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size));
unsigned num_components = nir_instr_as_load_const(instr)->def.num_components;
unsigned bit_size = nir_instr_as_load_const(instr)->def.bit_size;
RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, rc);
break;
}
case nir_instr_type_intrinsic: {
@ -552,12 +550,10 @@ void init_context(isel_context *ctx, nir_shader *shader)
break;
}
case nir_instr_type_ssa_undef: {
unsigned size = nir_instr_as_ssa_undef(instr)->def.num_components;
if (nir_instr_as_ssa_undef(instr)->def.bit_size == 64)
size *= 2;
else if (nir_instr_as_ssa_undef(instr)->def.bit_size == 1)
size *= lane_mask_size;
allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size));
unsigned num_components = nir_instr_as_ssa_undef(instr)->def.num_components;
unsigned bit_size = nir_instr_as_ssa_undef(instr)->def.bit_size;
RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, rc);
break;
}
case nir_instr_type_phi: {