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aco: implement nir_op_b2f16/nir_op_i2f16/nir_op_u2f16 

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
This commit is contained in:
Samuel Pitoiset 2020-04-03 15:26:15 +02:00
parent 3119f978e5
commit 67b567d0d0
2 changed files with 33 additions and 0 deletions
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30
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -2194,6 +2194,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
bld.vop1(aco_opcode::v_cvt_f64_f32, Definition(dst), src);
break;
}
case nir_op_i2f16: {
assert(dst.regClass() == v2b);
Temp tmp = bld.vop1(aco_opcode::v_cvt_f16_i16, bld.def(v1),
get_alu_src(ctx, instr->src[0]));
bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
break;
}
case nir_op_i2f32: {
assert(dst.size() == 1);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
@ -2219,6 +2226,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_u2f16: {
assert(dst.regClass() == v2b);
Temp tmp = bld.vop1(aco_opcode::v_cvt_f16_u16, bld.def(v1),
get_alu_src(ctx, instr->src[0]));
bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
break;
}
case nir_op_u2f32: {
assert(dst.size() == 1);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
@ -2480,6 +2494,22 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
break;
}
case nir_op_b2f16: {
Temp src = get_alu_src(ctx, instr->src[0]);
assert(src.regClass() == bld.lm);
if (dst.regClass() == s1) {
src = bool_to_scalar_condition(ctx, src);
bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3c00u), src);
} else if (dst.regClass() == v2b) {
Temp one = bld.copy(bld.def(v1), Operand(0x3c00u));
Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), tmp);
} else {
unreachable("Wrong destination register class for nir_op_b2f16.");
}
break;
}
case nir_op_b2f32: {
Temp src = get_alu_src(ctx, instr->src[0]);
assert(src.regClass() == bld.lm);

3
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@ -309,8 +309,10 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_op_f2f16_rtne:
case nir_op_f2f32:
case nir_op_f2f64:
case nir_op_u2f16:
case nir_op_u2f32:
case nir_op_u2f64:
case nir_op_i2f16:
case nir_op_i2f32:
case nir_op_i2f64:
case nir_op_pack_half_2x16:
@ -338,6 +340,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_op_f2u64:
case nir_op_b2i32:
case nir_op_b2b32:
case nir_op_b2f16:
case nir_op_b2f32:
case nir_op_mov:
type = ctx->divergent_vals[alu_instr->dest.dest.ssa.index] ? RegType::vgpr : RegType::sgpr;