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radv: fixup tess eval shader when combined. 

This fixes some access to the tess eval shader when it's combined
with geometry on gfx9.

This is a review of Bas's commit:
radv: Prevent crashing by accessing TES for VGT reuse depth.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-10-20 03:45:51 +01:00
parent e6acc20b6a
commit 5bc5e07d81
2 changed files with 23 additions and 6 deletions
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5
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -500,6 +500,11 @@ radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
if (pipeline->shaders[MESA_SHADER_GEOMETRY])
return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
} else if (stage == MESA_SHADER_TESS_EVAL) {
if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
if (pipeline->shaders[MESA_SHADER_GEOMETRY])
return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
}
return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
}

24
src/amd/vulkan/radv_pipeline.c
View File

@ -1173,9 +1173,13 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
&pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
&pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
struct ac_es_output_info *es_info;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
else
es_info = radv_pipeline_has_tess(pipeline) ?
&pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
&pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
/* Calculate the minimum size. */
unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
@ -1217,6 +1221,14 @@ radv_get_vertex_shader(struct radv_pipeline *pipeline)
return pipeline->shaders[MESA_SHADER_GEOMETRY];
}
static struct radv_shader_variant *
radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
{
if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
return pipeline->shaders[MESA_SHADER_TESS_EVAL];
return pipeline->shaders[MESA_SHADER_GEOMETRY];
}
static void
calculate_tess_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
@ -1309,7 +1321,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess->num_patches = num_patches;
tess->num_tcs_input_cp = num_tcs_input_cp;
struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
switch (tes->info.tes.primitive_mode) {
@ -1961,7 +1973,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
if (radv_pipeline_has_tess(pipeline)) {
/* SWITCH_ON_EOI must be set if PrimID is used. */
if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
radv_get_tess_eval_shader(pipeline)->info.tes.uses_prim_id)
pipeline->graphics.ia_switch_on_eoi = true;
}
@ -2044,7 +2056,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
pipeline->graphics.vtx_reuse_depth = 30;
if (radv_pipeline_has_tess(pipeline) &&
pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
pipeline->graphics.vtx_reuse_depth = 14;
}