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pan/mdg: Implement raw colourbuf loads on T720 

Uses a similar path to the fp16 cbuf loads on T760. It should make sense
given the symmetry with T860.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
This commit is contained in:
Alyssa Rosenzweig 2020-05-29 21:11:11 -04:00 committed by Marge Bot
parent 4f82aad7a2
commit 5a175e4a1b
3 changed files with 11 additions and 5 deletions
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1
src/panfrost/midgard/midgard.h
View File

@ -479,6 +479,7 @@ typedef enum {
/* Old version of midgard_op_ld_color_buffer_as_fp16, for T720 */
midgard_op_ld_color_buffer_as_fp16_old = 0x9D,
midgard_op_ld_color_buffer_32u_old = 0x9E,
/* The distinction between these ops is the alignment requirement /
* accompanying shift. Thus, the offset to ld_ubo_int4 is in 16-byte

14
src/panfrost/midgard/midgard_compile.c
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@ -1581,15 +1581,19 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
midgard_op_ld_color_buffer_as_fp16_old :
midgard_op_ld_color_buffer_as_fp16;
if (old_blend) {
ld.load_store.address = 1;
ld.load_store.arg_2 = 0x1E;
}
for (unsigned c = 4; c < 16; ++c)
ld.swizzle[0][c] = 0;
ld.dest_type = nir_type_float16;
if (old_blend) {
ld.load_store.address = 1;
ld.load_store.arg_2 = 0x1E;
}
} else if (old_blend) {
ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
ld.load_store.address = 16;
ld.load_store.arg_2 = 0x1E;
}
emit_mir_instruction(ctx, ld);

1
src/panfrost/midgard/midgard_ops.c
View File

@ -227,6 +227,7 @@ struct mir_ldst_op_props load_store_opcode_props[256] = {
[midgard_op_ld_vary_32u] = {"ld_vary_32u", M32},
[midgard_op_ld_color_buffer_32u] = {"ld_color_buffer_32u", M32},
[midgard_op_ld_color_buffer_32u_old] = {"ld_color_buffer_32u_old", M32},
[midgard_op_ld_color_buffer_as_fp16] = {"ld_color_buffer_as_fp16", M16},
[midgard_op_ld_color_buffer_as_fp16_old] = {"ld_color_buffer_as_fp16_old", M16 | LDST_SPECIAL_MASK},