pan/mdg: Set RA bounds for fp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
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@ -525,13 +525,25 @@ allocate_registers(compiler_context *ctx, bool *spilled)
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(size == 64) ? 3 : /* (1 << 3) = 8-byte */
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3; /* 8-bit todo */
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/* We can't cross xy/zw boundaries. TODO: vec8 can */
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if (size == 16)
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min_bound[dest] = 8;
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/* We don't have a swizzle for the conditional and we don't
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* want to muck with the conditional itself, so just force
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* alignment for now */
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if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op))
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if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) {
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min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */
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/* LCRA assumes bound >= alignment */
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min_bound[dest] = 16;
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}
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/* Since ld/st swizzles and masks are 32-bit only, we need them
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* aligned to enable final packing */
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if (ins->type == TAG_LOAD_STORE_4)
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min_alignment[dest] = MAX2(min_alignment[dest], 2);
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}
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for (unsigned i = 0; i < ctx->temp_count; ++i) {
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