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pan/mdg: Set RA bounds for fp16 

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
This commit is contained in:
Alyssa Rosenzweig 2020-05-11 15:07:25 -04:00 committed by Marge Bot
parent b91d71597e
commit 553c2cf16b
1 changed files with 13 additions and 1 deletions
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14
src/panfrost/midgard/midgard_ra.c
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@ -525,13 +525,25 @@ allocate_registers(compiler_context *ctx, bool *spilled)
(size == 64) ? 3 : /* (1 << 3) = 8-byte */
3; /* 8-bit todo */
/* We can't cross xy/zw boundaries. TODO: vec8 can */
if (size == 16)
min_bound[dest] = 8;
/* We don't have a swizzle for the conditional and we don't
* want to muck with the conditional itself, so just force
* alignment for now */
if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op))
if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->alu.op)) {
min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */
/* LCRA assumes bound >= alignment */
min_bound[dest] = 16;
}
/* Since ld/st swizzles and masks are 32-bit only, we need them
* aligned to enable final packing */
if (ins->type == TAG_LOAD_STORE_4)
min_alignment[dest] = MAX2(min_alignment[dest], 2);
}
for (unsigned i = 0; i < ctx->temp_count; ++i) {