i965: Fix up VS DP4 sequences to avoid dependency control.
This is recommended by the B-Spec. I wasn't able to measure any difference in ETQW.
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@ -54,6 +54,7 @@ DRIVER_SOURCES = \
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brw_gs_emit.c \
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brw_gs_state.c \
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brw_misc_state.c \
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brw_optimize.c \
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brw_program.c \
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brw_queryobj.c \
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brw_sf.c \
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@ -966,4 +966,9 @@ void brw_math_invert( struct brw_compile *p,
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void brw_set_src1( struct brw_instruction *insn,
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struct brw_reg reg );
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/* brw_optimize.c */
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void brw_optimize(struct brw_compile *p);
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#endif
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@ -0,0 +1,115 @@
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "main/macros.h"
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#include "shader/program.h"
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#include "shader/prog_parameter.h"
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#include "shader/prog_print.h"
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#include "brw_context.h"
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#include "brw_defines.h"
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#include "brw_eu.h"
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static GLboolean
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is_single_channel_dp4(struct brw_instruction *insn)
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{
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if (insn->header.opcode != BRW_OPCODE_DP4 ||
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insn->header.execution_size != BRW_EXECUTE_8 ||
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insn->header.access_mode != BRW_ALIGN_16 ||
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insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
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return GL_FALSE;
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if (!is_power_of_two(insn->bits1.da16.dest_writemask))
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return GL_FALSE;
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return GL_TRUE;
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}
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/**
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* Sets the dependency control fields on DP4 instructions.
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*
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* The hardware only tracks dependencies on a register basis, so when
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* you do:
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*
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* DP4 dst.x src1 src2
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* DP4 dst.y src1 src3
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* DP4 dst.z src1 src4
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* DP4 dst.w src1 src5
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*
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* It will wait to do the DP4 dst.y until the dst.x is resolved, etc.
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* We can examine our instruction stream and set the dependency
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* control fields to tell the hardware when to do it.
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*
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* We may want to extend this to other instructions that are used to
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* fill in a channel at a time of the destination register.
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*/
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static void
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brw_set_dp4_dependency_control(struct brw_compile *p)
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{
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int i;
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for (i = 1; i < p->nr_insn; i++) {
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struct brw_instruction *insn = &p->store[i];
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struct brw_instruction *prev = &p->store[i - 1];
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if (!is_single_channel_dp4(prev))
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continue;
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if (!is_single_channel_dp4(insn)) {
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i++;
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continue;
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}
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/* Only avoid hw dep control if the write masks are different
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* channels of one reg.
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*/
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if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
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continue;
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if (insn->bits1.da16.dest_reg_nr != prev->bits1.da16.dest_reg_nr)
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continue;
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/* Check if the second instruction depends on the previous one
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* for a src.
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*/
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if (insn->bits1.da1.src0_reg_file == BRW_GENERAL_REGISTER_FILE &&
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(insn->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
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insn->bits2.da1.src0_reg_nr == insn->bits1.da16.dest_reg_nr))
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continue;
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if (insn->bits1.da1.src1_reg_file == BRW_GENERAL_REGISTER_FILE &&
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(insn->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT ||
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insn->bits3.da1.src1_reg_nr == insn->bits1.da16.dest_reg_nr))
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continue;
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prev->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
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insn->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
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}
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}
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void
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brw_optimize(struct brw_compile *p)
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{
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brw_set_dp4_dependency_control(p);
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}
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@ -1825,6 +1825,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
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post_vs_emit(c, end_inst, last_inst);
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brw_optimize(p);
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if (INTEL_DEBUG & DEBUG_VS) {
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int i;
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