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freedreno/ir3/postsched: try to avoid (sy) syncs 

Similar to avoidance of `(ss)` syncs, it turns out to be helpful to
avoid `(sy)` syncs as well.  This helps us turn an tex, (sy)alu, tex,
(sy)alu sequence into tex, tex, (sy)alu, alu, which is a big win in
gfxbench gl_fill2.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4923>
This commit is contained in:
Rob Clark 2020-05-06 10:06:17 -07:00 committed by Marge Bot
parent 25f4fb346e
commit 488cf208d5
1 changed files with 19 additions and 2 deletions
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21
src/freedreno/ir3/ir3_postsched.c
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@ -62,6 +62,7 @@ struct ir3_postsched_ctx {
bool error;
int sfu_delay;
int tex_delay;
};
struct ir3_postsched_node {
@ -92,6 +93,12 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
list_addtail(&instr->node, &instr->block->instr_list);
struct ir3_postsched_node *n = instr->data;
dag_prune_head(ctx->dag, &n->dag);
if (is_meta(instr) && (instr->opc != OPC_META_TEX_PREFETCH))
return;
if (is_sfu(instr)) {
ctx->sfu_delay = 8;
} else if (check_src_cond(instr, is_sfu)) {
@ -100,8 +107,13 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
ctx->sfu_delay--;
}
struct ir3_postsched_node *n = instr->data;
dag_prune_head(ctx->dag, &n->dag);
if (is_tex_or_prefetch(instr)) {
ctx->tex_delay = 10;
} else if (check_src_cond(instr, is_tex_or_prefetch)) {
ctx->tex_delay = 0;
} else if (ctx->tex_delay > 0) {
ctx->tex_delay--;
}
}
static void
@ -135,6 +147,11 @@ would_sync(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
return true;
}
if (ctx->tex_delay) {
if (check_src_cond(instr, is_tex_or_prefetch))
return true;
}
return false;
}