From 488cf208d5d90b0f3b3c346e0abb92e71597202f Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 6 May 2020 10:06:17 -0700 Subject: [PATCH] freedreno/ir3/postsched: try to avoid (sy) syncs Similar to avoidance of `(ss)` syncs, it turns out to be helpful to avoid `(sy)` syncs as well. This helps us turn an tex, (sy)alu, tex, (sy)alu sequence into tex, tex, (sy)alu, alu, which is a big win in gfxbench gl_fill2. Signed-off-by: Rob Clark Part-of: --- src/freedreno/ir3/ir3_postsched.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/freedreno/ir3/ir3_postsched.c b/src/freedreno/ir3/ir3_postsched.c index 4535459efcf..238d937c805 100644 --- a/src/freedreno/ir3/ir3_postsched.c +++ b/src/freedreno/ir3/ir3_postsched.c @@ -62,6 +62,7 @@ struct ir3_postsched_ctx { bool error; int sfu_delay; + int tex_delay; }; struct ir3_postsched_node { @@ -92,6 +93,12 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) list_addtail(&instr->node, &instr->block->instr_list); + struct ir3_postsched_node *n = instr->data; + dag_prune_head(ctx->dag, &n->dag); + + if (is_meta(instr) && (instr->opc != OPC_META_TEX_PREFETCH)) + return; + if (is_sfu(instr)) { ctx->sfu_delay = 8; } else if (check_src_cond(instr, is_sfu)) { @@ -100,8 +107,13 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) ctx->sfu_delay--; } - struct ir3_postsched_node *n = instr->data; - dag_prune_head(ctx->dag, &n->dag); + if (is_tex_or_prefetch(instr)) { + ctx->tex_delay = 10; + } else if (check_src_cond(instr, is_tex_or_prefetch)) { + ctx->tex_delay = 0; + } else if (ctx->tex_delay > 0) { + ctx->tex_delay--; + } } static void @@ -135,6 +147,11 @@ would_sync(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) return true; } + if (ctx->tex_delay) { + if (check_src_cond(instr, is_tex_or_prefetch)) + return true; + } + return false; }