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r600g/compute: always CONTEXT_CONTROL packet at start of CS 

It's required.  The CP uses this to properly allocate new
contexts.  Also do a CS partial flush since we are updating
CONFIG regs which are single state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Alex Deucher 2012-10-23 11:30:31 -04:00
parent 4a93414985
commit 480e146305
2 changed files with 10 additions and 0 deletions
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9
src/gallium/drivers/r600/evergreen_compute.c
View File

@ -626,6 +626,15 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
r600_init_command_buffer(cb, 256);
cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
/* This must be first. */
r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
r600_store_value(cb, 0x80000000);
r600_store_value(cb, 0x80000000);
/* We're setting config registers here. */
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
switch (ctx->family) {
case CHIP_CEDAR:
default:

1
src/gallium/drivers/r600/evergreend.h
View File

@ -43,6 +43,7 @@
#define EVERGREEN_CTL_CONST_OFFSET 0x0003CFF0
#define EVERGREEN_CTL_CONST_END 0x0003FF0C
#define EVENT_TYPE_CS_PARTIAL_FLUSH 0x07
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16