From 480e1463057c70ca1b197cbba5a9b1c153d8b052 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 23 Oct 2012 11:30:31 -0400 Subject: [PATCH] r600g/compute: always CONTEXT_CONTROL packet at start of CS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's required. The CP uses this to properly allocate new contexts. Also do a CS partial flush since we are updating CONFIG regs which are single state. Signed-off-by: Alex Deucher Reviewed-by: Marek Olšák Reviewed-by: Tom Stellard --- src/gallium/drivers/r600/evergreen_compute.c | 9 +++++++++ src/gallium/drivers/r600/evergreend.h | 1 + 2 files changed, 10 insertions(+) diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index 25263f3b013..ce17d3a61ec 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -626,6 +626,15 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx) r600_init_command_buffer(cb, 256); cb->pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE; + /* This must be first. */ + r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); + r600_store_value(cb, 0x80000000); + r600_store_value(cb, 0x80000000); + + /* We're setting config registers here. */ + r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); + r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + switch (ctx->family) { case CHIP_CEDAR: default: diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index d10ec7f2af5..98df83de918 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -43,6 +43,7 @@ #define EVERGREEN_CTL_CONST_OFFSET 0x0003CFF0 #define EVERGREEN_CTL_CONST_END 0x0003FF0C +#define EVENT_TYPE_CS_PARTIAL_FLUSH 0x07 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 #define EVENT_TYPE_ZPASS_DONE 0x15 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16