ac/surface: move tile_swizzle to ac_surface and document it
Gfx9 will use it too. Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -716,7 +716,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
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AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
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AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
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AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
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surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
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assert(AddrBaseSwizzleOut.tileSwizzle <=
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u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
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surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
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}
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return 0;
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}
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@ -97,7 +97,6 @@ struct legacy_surf_layout {
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unsigned depth_adjusted:1;
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unsigned stencil_adjusted:1;
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uint8_t tile_swizzle;
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struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
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struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
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uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
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@ -168,6 +167,21 @@ struct radeon_surf {
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* they will be treated as hints (e.g. bankw, bankh) and might be
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* changed by the calculator.
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*/
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/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
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* The value is the same for all mipmap levels. Supported tile modes:
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* - GFX6: Only macro tiling.
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* - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
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*
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* Only these surfaces are allowed to set it:
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* - color (if it doesn't have to be displayable)
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* - DCC (same tile swizzle as color)
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* - FMASK
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* - CMASK if it's TC-compatible or if the gen is GFX9
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* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
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*/
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uint8_t tile_swizzle;
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uint64_t surf_size;
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uint64_t dcc_size;
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uint64_t htile_size;
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@ -3010,7 +3010,7 @@ radv_initialise_color_surface(struct radv_device *device,
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cb->cb_color_base = va >> 8;
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if (device->physical_device->rad_info.chip_class < GFX9)
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cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
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cb->cb_color_base |= iview->image->surface.tile_swizzle;
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/* CMASK variables */
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va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
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va += iview->image->cmask.offset;
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@ -3020,7 +3020,7 @@ radv_initialise_color_surface(struct radv_device *device,
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va += iview->image->dcc_offset;
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cb->cb_dcc_base = va >> 8;
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if (device->physical_device->rad_info.chip_class < GFX9)
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cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
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cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
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uint32_t max_slice = radv_surface_layer_count(iview);
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cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
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@ -3037,7 +3037,7 @@ radv_initialise_color_surface(struct radv_device *device,
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va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
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cb->cb_color_fmask = va >> 8;
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if (device->physical_device->rad_info.chip_class < GFX9)
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cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
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cb->cb_color_fmask |= iview->image->surface.tile_swizzle;
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} else {
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cb->cb_color_fmask = cb->cb_color_base;
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}
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@ -218,7 +218,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
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state[0] = va >> 8;
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if (chip_class < GFX9)
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state[0] |= image->surface.u.legacy.tile_swizzle;
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state[0] |= image->surface.tile_swizzle;
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state[1] &= C_008F14_BASE_ADDRESS_HI;
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state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
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state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
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@ -235,7 +235,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
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state[6] |= S_008F28_COMPRESSION_EN(1);
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state[7] = meta_va >> 8;
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if (chip_class < GFX9)
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state[7] |= image->surface.u.legacy.tile_swizzle;
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state[7] |= image->surface.tile_swizzle;
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}
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}
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@ -484,7 +484,7 @@ si_make_texture_descriptor(struct radv_device *device,
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fmask_state[0] = va >> 8;
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if (device->physical_device->rad_info.chip_class < GFX9)
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fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
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fmask_state[0] |= image->surface.tile_swizzle;
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fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
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S_008F14_DATA_FORMAT_GFX6(fmask_format) |
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S_008F14_NUM_FORMAT_GFX6(num_format);
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