diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 26f3729adf9..4647ce46c59 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -716,7 +716,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 		AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
 		AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
 		AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
-		surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
+
+		assert(AddrBaseSwizzleOut.tileSwizzle <=
+		       u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
+		surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
 	}
 	return 0;
 }
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 3eaef639aad..ee96003f661 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -97,7 +97,6 @@ struct legacy_surf_layout {
     unsigned                    depth_adjusted:1;
     unsigned                    stencil_adjusted:1;
 
-    uint8_t                     tile_swizzle;
     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
@@ -168,6 +167,21 @@ struct radeon_surf {
      * they will be treated as hints (e.g. bankw, bankh) and might be
      * changed by the calculator.
      */
+
+    /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
+     * The value is the same for all mipmap levels. Supported tile modes:
+     * - GFX6: Only macro tiling.
+     * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
+     *
+     * Only these surfaces are allowed to set it:
+     * - color (if it doesn't have to be displayable)
+     * - DCC (same tile swizzle as color)
+     * - FMASK
+     * - CMASK if it's TC-compatible or if the gen is GFX9
+     * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
+     */
+    uint8_t                     tile_swizzle;
+
     uint64_t                    surf_size;
     uint64_t                    dcc_size;
     uint64_t                    htile_size;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 13fb19cf48b..9a34a20082d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3010,7 +3010,7 @@ radv_initialise_color_surface(struct radv_device *device,
 
 	cb->cb_color_base = va >> 8;
 	if (device->physical_device->rad_info.chip_class < GFX9)
-		cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle;
+		cb->cb_color_base |= iview->image->surface.tile_swizzle;
 	/* CMASK variables */
 	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
 	va += iview->image->cmask.offset;
@@ -3020,7 +3020,7 @@ radv_initialise_color_surface(struct radv_device *device,
 	va += iview->image->dcc_offset;
 	cb->cb_dcc_base = va >> 8;
 	if (device->physical_device->rad_info.chip_class < GFX9)
-		cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
+		cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
 
 	uint32_t max_slice = radv_surface_layer_count(iview);
 	cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
@@ -3037,7 +3037,7 @@ radv_initialise_color_surface(struct radv_device *device,
 		va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
 		cb->cb_color_fmask = va >> 8;
 		if (device->physical_device->rad_info.chip_class < GFX9)
-			cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle;
+			cb->cb_color_fmask |= iview->image->surface.tile_swizzle;
 	} else {
 		cb->cb_color_fmask = cb->cb_color_base;
 	}
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ce1ee24036e..4b47e17af0a 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -218,7 +218,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
 	state[0] = va >> 8;
 	if (chip_class < GFX9)
-		state[0] |= image->surface.u.legacy.tile_swizzle;
+		state[0] |= image->surface.tile_swizzle;
 	state[1] &= C_008F14_BASE_ADDRESS_HI;
 	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 	state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
@@ -235,7 +235,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 			state[6] |= S_008F28_COMPRESSION_EN(1);
 			state[7] = meta_va >> 8;
 			if (chip_class < GFX9)
-				state[7] |= image->surface.u.legacy.tile_swizzle;
+				state[7] |= image->surface.tile_swizzle;
 		}
 	}
 
@@ -484,7 +484,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
 		fmask_state[0] = va >> 8;
 		if (device->physical_device->rad_info.chip_class < GFX9)
-			fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
+			fmask_state[0] |= image->surface.tile_swizzle;
 		fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
 			S_008F14_DATA_FORMAT_GFX6(fmask_format) |
 			S_008F14_NUM_FORMAT_GFX6(num_format);