diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c
index e605e1d5e7b..3936c47c4ca 100644
--- a/src/panfrost/bifrost/bi_ra.c
+++ b/src/panfrost/bifrost/bi_ra.c
@@ -366,6 +366,7 @@ bi_register_allocate(bi_context *ctx)
                 unsigned both = BI_DATA_REG_SRC | BI_DATA_REG_DEST;
                 if ((props & both) != both) continue;
 
+                assert(ins->src[0] & PAN_IS_REG);
                 bi_rewrite_uses(ctx, ins->dest, 0, ins->src[0], 0);
                 ins->dest = ins->src[0];
         }
diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index d072cd16da0..ddcba5c9a7f 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -2052,11 +2052,12 @@ emit_texc(bi_context *ctx, nir_tex_instr *instr)
                 }
         }
 
-        /* Allocate data registers contiguously */
+        /* Allocate data registers contiguously. Index must not be marked SSA
+         * due to a quirk of RA for tied operands, could be fixed eventually */
         bi_instruction combine = {
                 .type = BI_COMBINE,
                 .dest_type = nir_type_uint32,
-                .dest = bi_make_temp(ctx),
+                .dest = bi_make_temp_reg(ctx),
                 .src_types = {
                         nir_type_uint32, nir_type_uint32,
                         nir_type_uint32, nir_type_uint32,
@@ -2082,7 +2083,7 @@ emit_texc(bi_context *ctx, nir_tex_instr *instr)
                 for (unsigned i = 0; i < dreg_index; ++i)
                         tex.swizzle[0][i] = i;
         } else {
-                tex.src[0] = tex.dest;
+                tex.src[0] = bi_make_temp_reg(ctx);
         }
 
         /* Pass the texture operation descriptor in src2 */