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pan/va: Model LEA_TEX_IMM more accurately 

The unknown field is a descriptor type, which we model as an opcode2 since it's
a fixed constant. This allows us to disambiguate LEA_TEX_IMM from LEA_ATTR_IMM.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15461>
This commit is contained in:
Alyssa Rosenzweig 2022-03-17 16:03:42 -04:00 committed by Marge Bot
parent 17caccd15d
commit 459c6ac23f
4 changed files with 8 additions and 5 deletions
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4
src/panfrost/bifrost/valhall/ISA.xml
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@ -850,7 +850,7 @@
<imm name="table" start="16" size="4"/>
</ins>
<ins name="LEA_TEX_IMM" title="Load effective address of image texel" opcode="0x67" unit="LS">
<ins name="LEA_TEX_IMM" title="Load effective address of image texel" opcode="0x67" opcode2="1" unit="LS">
<desc>
Load the effective address of a texel from the image specified with the
given immediate index. Returns three staging register: the low/high
@ -864,8 +864,8 @@
<vecsize/>
<slot/>
<sr_count/>
<mod name="descriptor_type" start="128" size="1" implied="true"/>
<sr write="true"/>
<imm name="unk" start="36" size="4"/>
<src>X/Y coordinates (16:16)</src>
<src>Z/W coordinates (16:16)</src>
<imm name="table" start="16" size="4"/>

2
src/panfrost/bifrost/valhall/disasm.py
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@ -145,7 +145,7 @@ va_disasm_instr(FILE *fp, uint64_t instr)
% endif
fputs("${op.name}", fp);
% for mod in op.modifiers:
% if mod.name not in ["left", "staging_register_count", "staging_register_write_count"]:
% if mod.name not in ["left", "descriptor_type", "staging_register_count", "staging_register_write_count"]:
% if mod.is_enum:
fputs(valhall_${safe_name(mod.enum)}[(instr >> ${mod.start}) & ${hex((1 << mod.size) - 1)}], fp);
% else:

4
src/panfrost/bifrost/valhall/test/assembler-cases.txt
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@ -109,8 +109,8 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
44 00 46 32 28 40 71 78 ST_CVT.v4.f32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 34 28 40 71 78 ST_CVT.v4.s32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 36 28 40 71 78 ST_CVT.v4.u32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x1
7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x0
7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, table:0x2, index:0x1
7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, table:0x2, index:0x0
82 81 00 28 f4 82 6a 00 LD_BUFFER.i64.unsigned.slot0 @r2:r3, u2, u1
80 81 00 68 f4 80 6a 00 LD_BUFFER.i64.unsigned.slot1 @r0:r1, u0, u1
84 81 00 a8 f4 a6 6a 00 LD_BUFFER.i64.unsigned.slot2 @r38:r39, u4, u1

3
src/panfrost/bifrost/valhall/valhall.py
View File

@ -199,6 +199,9 @@ class Instruction:
if name.startswith("LOAD.i") or name.startswith("STORE.i") or name.startswith("LD_BUFFER.i"):
self.secondary_shift = 27 # Alias with memory_size
self.secondary_mask = 0x7
if "descriptor_type" in [x.name for x in self.modifiers]:
self.secondary_mask = 0x3
self.secondary_shift = 37
assert(len(dests) == 0 or not staging)
assert(not opcode2 or (opcode2 & self.secondary_mask) == opcode2)