From 459c6ac23fc7e01cab37a0e8cd5c9de23e4203b7 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 17 Mar 2022 16:03:42 -0400 Subject: [PATCH] pan/va: Model LEA_TEX_IMM more accurately The unknown field is a descriptor type, which we model as an opcode2 since it's a fixed constant. This allows us to disambiguate LEA_TEX_IMM from LEA_ATTR_IMM. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/bifrost/valhall/ISA.xml | 4 ++-- src/panfrost/bifrost/valhall/disasm.py | 2 +- src/panfrost/bifrost/valhall/test/assembler-cases.txt | 4 ++-- src/panfrost/bifrost/valhall/valhall.py | 3 +++ 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml index d02560f6243..f272bc3eef0 100644 --- a/src/panfrost/bifrost/valhall/ISA.xml +++ b/src/panfrost/bifrost/valhall/ISA.xml @@ -850,7 +850,7 @@ - + Load the effective address of a texel from the image specified with the given immediate index. Returns three staging register: the low/high @@ -864,8 +864,8 @@ + - X/Y coordinates (16:16) Z/W coordinates (16:16) diff --git a/src/panfrost/bifrost/valhall/disasm.py b/src/panfrost/bifrost/valhall/disasm.py index 11822c1affc..8bd59561ca5 100644 --- a/src/panfrost/bifrost/valhall/disasm.py +++ b/src/panfrost/bifrost/valhall/disasm.py @@ -145,7 +145,7 @@ va_disasm_instr(FILE *fp, uint64_t instr) % endif fputs("${op.name}", fp); % for mod in op.modifiers: -% if mod.name not in ["left", "staging_register_count", "staging_register_write_count"]: +% if mod.name not in ["left", "descriptor_type", "staging_register_count", "staging_register_write_count"]: % if mod.is_enum: fputs(valhall_${safe_name(mod.enum)}[(instr >> ${mod.start}) & ${hex((1 << mod.size) - 1)}], fp); % else: diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt index b618397fd52..dd4745803b5 100644 --- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt +++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt @@ -109,8 +109,8 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1 44 00 46 32 28 40 71 78 ST_CVT.v4.f32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2 44 00 46 34 28 40 71 78 ST_CVT.v4.s32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2 44 00 46 36 28 40 71 78 ST_CVT.v4.u32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2 -7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x1 -7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x0 +7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, table:0x2, index:0x1 +7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, table:0x2, index:0x0 82 81 00 28 f4 82 6a 00 LD_BUFFER.i64.unsigned.slot0 @r2:r3, u2, u1 80 81 00 68 f4 80 6a 00 LD_BUFFER.i64.unsigned.slot1 @r0:r1, u0, u1 84 81 00 a8 f4 a6 6a 00 LD_BUFFER.i64.unsigned.slot2 @r38:r39, u4, u1 diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py index dfc31b38be3..17b8ecc53eb 100644 --- a/src/panfrost/bifrost/valhall/valhall.py +++ b/src/panfrost/bifrost/valhall/valhall.py @@ -199,6 +199,9 @@ class Instruction: if name.startswith("LOAD.i") or name.startswith("STORE.i") or name.startswith("LD_BUFFER.i"): self.secondary_shift = 27 # Alias with memory_size self.secondary_mask = 0x7 + if "descriptor_type" in [x.name for x in self.modifiers]: + self.secondary_mask = 0x3 + self.secondary_shift = 37 assert(len(dests) == 0 or not staging) assert(not opcode2 or (opcode2 & self.secondary_mask) == opcode2)