i965: Add support for rendering to depthbuffer mipmap levels > 0.
Fixes GL_ARB_depth_texture/fbo-clear-formats GL_EXT_packed_depth_stencil/fbo-clear-formats
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@ -247,6 +247,7 @@ static void emit_depthbuffer(struct brw_context *brw)
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} else {
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struct intel_region *region = irb->region;
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unsigned int format;
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uint32_t tile_x, tile_y, offset;
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switch (region->cpp) {
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case 2:
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@ -263,7 +264,8 @@ static void emit_depthbuffer(struct brw_context *brw)
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return;
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}
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assert(region->tiling != I915_TILING_X);
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offset = intel_region_tile_offsets(region, &tile_x, &tile_y);
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assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
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BEGIN_BATCH(len);
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@ -275,14 +277,16 @@ static void emit_depthbuffer(struct brw_context *brw)
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(BRW_SURFACE_2D << 29));
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OUT_RELOC(region->buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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0);
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offset);
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OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
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((region->width - 1) << 6) |
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((region->height - 1) << 19));
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OUT_BATCH(0);
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if (intel->is_g4x || intel->gen >= 5)
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OUT_BATCH(0);
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OUT_BATCH(tile_x | (tile_y << 16));
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else
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assert(tile_x == 0 && tile_y == 0);
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if (intel->gen >= 6)
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OUT_BATCH(0);
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@ -450,6 +450,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
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struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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struct intel_region *region = irb->region;
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struct brw_surface_state *surf;
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uint32_t tile_x, tile_y;
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surf = brw_state_batch(brw, sizeof(*surf), 32,
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&brw->wm.surf_offset[unit]);
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@ -488,36 +489,18 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
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}
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surf->ss0.surface_type = BRW_SURFACE_2D;
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if (region->tiling == I915_TILING_NONE) {
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surf->ss1.base_addr = (region->draw_x +
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region->draw_y * region->pitch) * region->cpp;
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} else {
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uint32_t tile_base, tile_x, tile_y;
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uint32_t pitch = region->pitch * region->cpp;
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/* reloc */
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surf->ss1.base_addr = intel_region_tile_offsets(region, &tile_x, &tile_y);
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surf->ss1.base_addr += region->buffer->offset; /* reloc */
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if (region->tiling == I915_TILING_X) {
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tile_x = region->draw_x % (512 / region->cpp);
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tile_y = region->draw_y % 8;
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tile_base = ((region->draw_y / 8) * (8 * pitch));
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tile_base += (region->draw_x - tile_x) / (512 / region->cpp) * 4096;
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} else {
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/* Y */
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tile_x = region->draw_x % (128 / region->cpp);
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tile_y = region->draw_y % 32;
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tile_base = ((region->draw_y / 32) * (32 * pitch));
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tile_base += (region->draw_x - tile_x) / (128 / region->cpp) * 4096;
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}
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assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
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assert(tile_x % 4 == 0);
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assert(tile_y % 2 == 0);
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/* Note that the low bits of these fields are missing, so
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* there's the possibility of getting in trouble.
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*/
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surf->ss1.base_addr = tile_base;
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assert(tile_x % 4 == 0);
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assert(tile_y % 2 == 0);
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surf->ss5.x_offset = tile_x / 4;
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surf->ss5.y_offset = tile_y / 2;
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}
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surf->ss1.base_addr += region->buffer->offset; /* reloc */
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surf->ss2.width = rb->Width - 1;
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surf->ss2.height = rb->Height - 1;
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@ -524,3 +524,38 @@ intel_region_buffer(struct intel_context *intel,
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return region->buffer;
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}
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/**
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* Rendering to tiled buffers requires that the base address of the
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* buffer be aligned to a page boundary. We generally render to
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* textures by pointing the surface at the mipmap image level, which
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* may not be aligned to a tile boundary.
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*
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* This function returns an appropriately-aligned base offset
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* according to the tiling restrictions, plus any required x/y offset
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* from there.
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*/
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uint32_t
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intel_region_tile_offsets(struct intel_region *region,
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uint32_t *tile_x,
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uint32_t *tile_y)
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{
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uint32_t pitch = region->pitch * region->cpp;
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if (region->tiling == I915_TILING_NONE) {
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*tile_x = 0;
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*tile_y = 0;
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return region->draw_x * region->cpp + region->draw_y * pitch;
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} else if (region->tiling == I915_TILING_X) {
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*tile_x = region->draw_x % (512 / region->cpp);
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*tile_y = region->draw_y % 8;
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return ((region->draw_y / 8) * (8 * pitch) +
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(region->draw_x - *tile_x) / (512 / region->cpp) * 4096);
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} else {
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assert(region->tiling == I915_TILING_Y);
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*tile_x = region->draw_x % (128 / region->cpp);
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*tile_y = region->draw_y % 32;
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return ((region->draw_y / 32) * (32 * pitch) +
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(region->draw_x - *tile_x) / (128 / region->cpp) * 4096);
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}
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}
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@ -142,6 +142,10 @@ drm_intel_bo *intel_region_buffer(struct intel_context *intel,
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struct intel_region *region,
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GLuint flag);
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uint32_t intel_region_tile_offsets(struct intel_region *region,
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uint32_t *tile_x,
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uint32_t *tile_y);
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void _mesa_copy_rect(GLubyte * dst,
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GLuint cpp,
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GLuint dst_pitch,
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