From 3d62a41dcc050c07a78397b7693b2a5c58abf583 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Thu, 14 Jul 2022 11:33:19 -0700 Subject: [PATCH] freedreno/ir3: Enable core NIR's 16-bit ALU optimizations. In addition to hopefully generating shorter code, this optimizes out a comparison of a mediump-cast value in dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment passed through ANGLE, and allows the test to pass. We believe it to be a test bug, but emitting better code like apparently everyone else does is also a fine result. No change on GLES gfxbench shaders. Fixes: #6585 Part-of: --- src/freedreno/ir3/ir3_compiler.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index e7008be2034..00b11632154 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -292,6 +292,12 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id, compiler->nir_options.force_indirect_unrolling = nir_var_all; } + /* 16-bit ALU op generation is mostly controlled by frontend compiler options, but + * this core NIR option enables some optimizations of 16-bit operations. + */ + if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16)) + compiler->nir_options.support_16bit_alu = true; + if (!options->disable_cache) ir3_disk_cache_init(compiler);