radeonsi: shorten slot masks to 32 bits
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
0954d5e982
commit
3acaefb1bb
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@ -243,14 +243,14 @@ si_flush_depth_textures(struct si_context *sctx,
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struct si_textures_info *textures)
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{
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unsigned i;
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uint64_t mask = textures->depth_texture_mask;
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unsigned mask = textures->depth_texture_mask;
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while (mask) {
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struct pipe_sampler_view *view;
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struct si_sampler_view *sview;
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struct r600_texture *tex;
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i = u_bit_scan64(&mask);
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i = u_bit_scan(&mask);
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view = textures->views.views[i];
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assert(view);
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@ -326,13 +326,13 @@ si_decompress_sampler_color_textures(struct si_context *sctx,
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struct si_textures_info *textures)
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{
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unsigned i;
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uint64_t mask = textures->compressed_colortex_mask;
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unsigned mask = textures->compressed_colortex_mask;
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while (mask) {
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struct pipe_sampler_view *view;
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struct r600_texture *tex;
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i = u_bit_scan64(&mask);
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i = u_bit_scan(&mask);
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view = textures->views.views[i];
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assert(view);
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@ -352,13 +352,13 @@ si_decompress_image_color_textures(struct si_context *sctx,
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struct si_images_info *images)
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{
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unsigned i;
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uint64_t mask = images->compressed_colortex_mask;
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unsigned mask = images->compressed_colortex_mask;
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while (mask) {
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const struct pipe_image_view *view;
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struct r600_texture *tex;
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i = u_bit_scan64(&mask);
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i = u_bit_scan(&mask);
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view = &images->views[i];
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assert(view->resource->target != PIPE_BUFFER);
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@ -110,7 +110,7 @@ static void si_init_descriptors(struct si_descriptors *desc,
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desc->list = CALLOC(num_elements, element_dw_size * 4);
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desc->element_dw_size = element_dw_size;
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desc->num_elements = num_elements;
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desc->dirty_mask = num_elements == 64 ? ~0llu : (1llu << num_elements) - 1;
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desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
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desc->shader_userdata_offset = shader_userdata_index * 4;
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if (ce_offset) {
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@ -210,7 +210,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
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while(desc->dirty_mask) {
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int begin, count;
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u_bit_scan_consecutive_range64(&desc->dirty_mask, &begin,
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u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
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&count);
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begin *= desc->element_dw_size;
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@ -276,11 +276,11 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
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static void si_sampler_views_begin_new_cs(struct si_context *sctx,
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struct si_sampler_views *views)
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{
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uint64_t mask = views->desc.enabled_mask;
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unsigned mask = views->desc.enabled_mask;
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/* Add buffers to the CS. */
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while (mask) {
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int i = u_bit_scan64(&mask);
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int i = u_bit_scan(&mask);
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si_sampler_view_add_buffer(sctx, views->views[i]->texture);
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}
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@ -329,16 +329,16 @@ static void si_set_sampler_view(struct si_context *sctx,
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views->sampler_states[slot], 4*4);
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}
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views->desc.enabled_mask |= 1llu << slot;
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views->desc.enabled_mask |= 1u << slot;
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} else {
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pipe_sampler_view_reference(&views->views[slot], NULL);
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memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
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/* Only clear the lower dwords of FMASK. */
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memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
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views->desc.enabled_mask &= ~(1llu << slot);
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views->desc.enabled_mask &= ~(1u << slot);
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}
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views->desc.dirty_mask |= 1llu << slot;
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views->desc.dirty_mask |= 1u << slot;
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}
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static bool is_compressed_colortex(struct r600_texture *rtex)
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@ -363,8 +363,8 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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unsigned slot = start + i;
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if (!views || !views[i]) {
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samplers->depth_texture_mask &= ~(1llu << slot);
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samplers->compressed_colortex_mask &= ~(1llu << slot);
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samplers->depth_texture_mask &= ~(1u << slot);
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samplers->compressed_colortex_mask &= ~(1u << slot);
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si_set_sampler_view(sctx, &samplers->views, slot, NULL);
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continue;
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}
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@ -376,18 +376,18 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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(struct r600_texture*)views[i]->texture;
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if (rtex->is_depth && !rtex->is_flushing_texture) {
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samplers->depth_texture_mask |= 1llu << slot;
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samplers->depth_texture_mask |= 1u << slot;
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} else {
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samplers->depth_texture_mask &= ~(1llu << slot);
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samplers->depth_texture_mask &= ~(1u << slot);
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}
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if (is_compressed_colortex(rtex)) {
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samplers->compressed_colortex_mask |= 1llu << slot;
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samplers->compressed_colortex_mask |= 1u << slot;
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} else {
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samplers->compressed_colortex_mask &= ~(1llu << slot);
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samplers->compressed_colortex_mask &= ~(1u << slot);
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}
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} else {
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samplers->depth_texture_mask &= ~(1llu << slot);
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samplers->compressed_colortex_mask &= ~(1llu << slot);
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samplers->depth_texture_mask &= ~(1u << slot);
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samplers->compressed_colortex_mask &= ~(1u << slot);
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}
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}
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}
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@ -395,19 +395,19 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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static void
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si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
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{
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uint64_t mask = samplers->views.desc.enabled_mask;
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unsigned mask = samplers->views.desc.enabled_mask;
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while (mask) {
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int i = u_bit_scan64(&mask);
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int i = u_bit_scan(&mask);
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struct pipe_resource *res = samplers->views.views[i]->texture;
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if (res && res->target != PIPE_BUFFER) {
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struct r600_texture *rtex = (struct r600_texture *)res;
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if (is_compressed_colortex(rtex)) {
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samplers->compressed_colortex_mask |= 1llu << i;
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samplers->compressed_colortex_mask |= 1u << i;
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} else {
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samplers->compressed_colortex_mask &= ~(1llu << i);
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samplers->compressed_colortex_mask &= ~(1u << i);
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}
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}
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}
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@ -457,13 +457,13 @@ si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *imag
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static void
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si_disable_shader_image(struct si_images_info *images, unsigned slot)
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{
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if (images->desc.enabled_mask & (1llu << slot)) {
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if (images->desc.enabled_mask & (1u << slot)) {
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pipe_resource_reference(&images->views[slot].resource, NULL);
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images->compressed_colortex_mask &= ~(1 << slot);
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memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
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images->desc.enabled_mask &= ~(1llu << slot);
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images->desc.dirty_mask |= 1llu << slot;
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images->desc.enabled_mask &= ~(1u << slot);
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images->desc.dirty_mask |= 1u << slot;
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}
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}
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@ -543,18 +543,18 @@ si_set_shader_images(struct pipe_context *pipe, unsigned shader,
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NULL);
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}
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images->desc.enabled_mask |= 1llu << slot;
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images->desc.dirty_mask |= 1llu << slot;
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images->desc.enabled_mask |= 1u << slot;
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images->desc.dirty_mask |= 1u << slot;
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}
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}
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static void
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si_images_update_compressed_colortex_mask(struct si_images_info *images)
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{
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uint64_t mask = images->desc.enabled_mask;
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unsigned mask = images->desc.enabled_mask;
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while (mask) {
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int i = u_bit_scan64(&mask);
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int i = u_bit_scan(&mask);
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struct pipe_resource *res = images->views[i].resource;
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if (res && res->target != PIPE_BUFFER) {
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@ -602,7 +602,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
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continue;
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memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
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desc->dirty_mask |= 1llu << slot;
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desc->dirty_mask |= 1u << slot;
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}
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}
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@ -638,11 +638,11 @@ static void si_release_buffer_resources(struct si_buffer_resources *buffers)
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static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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struct si_buffer_resources *buffers)
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{
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uint64_t mask = buffers->desc.enabled_mask;
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unsigned mask = buffers->desc.enabled_mask;
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/* Add buffers to the CS. */
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while (mask) {
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int i = u_bit_scan64(&mask);
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int i = u_bit_scan(&mask);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffers->buffers[i],
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@ -835,14 +835,14 @@ void si_set_constant_buffer(struct si_context *sctx,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1llu << slot;
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buffers->desc.enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1llu << slot);
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buffers->desc.enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1llu << slot;
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buffers->desc.dirty_mask |= 1u << slot;
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}
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static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
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@ -879,7 +879,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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if (!sbuffer || !sbuffer->buffer) {
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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memset(desc, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1llu << slot);
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buffers->desc.enabled_mask &= ~(1u << slot);
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continue;
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}
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@ -900,10 +900,9 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1llu << slot;
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buffers->desc.dirty_mask |= 1llu << slot;
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buffers->desc.enabled_mask |= 1u << slot;
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buffers->desc.dirty_mask |= 1u << slot;
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}
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}
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/* RING BUFFERS */
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@ -991,14 +990,14 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1llu << slot;
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buffers->desc.enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1llu << slot);
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buffers->desc.enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1llu << slot;
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buffers->desc.dirty_mask |= 1u << slot;
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}
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/* STREAMOUT BUFFERS */
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@ -1088,26 +1087,25 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1llu << bufidx;
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buffers->desc.enabled_mask |= 1u << bufidx;
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} else {
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0,
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sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx],
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NULL);
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buffers->desc.enabled_mask &= ~(1llu << bufidx);
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buffers->desc.enabled_mask &= ~(1u << bufidx);
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}
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buffers->desc.dirty_mask |= 1llu << bufidx;
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buffers->desc.dirty_mask |= 1u << bufidx;
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}
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for (; i < old_num_targets; i++) {
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bufidx = SI_VS_STREAMOUT_BUF0 + i;
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx], NULL);
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buffers->desc.enabled_mask &= ~(1llu << bufidx);
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buffers->desc.dirty_mask |= 1llu << bufidx;
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buffers->desc.enabled_mask &= ~(1u << bufidx);
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buffers->desc.dirty_mask |= 1u << bufidx;
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}
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}
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static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
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@ -1171,15 +1169,15 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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struct pipe_resource *buf,
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uint64_t old_va)
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{
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uint64_t mask = buffers->desc.enabled_mask;
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unsigned mask = buffers->desc.enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan64(&mask);
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unsigned i = u_bit_scan(&mask);
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if (buffers->buffers[i] == buf) {
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si_desc_reset_buffer_offset(&sctx->b.b,
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buffers->desc.list + i*4,
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old_va, buf);
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buffers->desc.dirty_mask |= 1llu << i;
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buffers->desc.dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)buf,
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@ -1271,16 +1269,16 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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uint64_t mask = views->desc.enabled_mask;
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unsigned mask = views->desc.enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan64(&mask);
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unsigned i = u_bit_scan(&mask);
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if (views->views[i]->texture == buf) {
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si_desc_reset_buffer_offset(ctx,
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views->desc.list +
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i * 16 + 4,
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old_va, buf);
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views->desc.dirty_mask |= 1llu << i;
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views->desc.dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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rbuffer, RADEON_USAGE_READ,
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@ -1301,7 +1299,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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si_desc_reset_buffer_offset(
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ctx, images->desc.list + i * 8 + 4,
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old_va, buf);
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images->desc.dirty_mask |= 1llu << i;
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images->desc.dirty_mask |= 1u << i;
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radeon_add_to_buffer_list(
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&sctx->b, &sctx->b.gfx, rbuffer,
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@ -137,8 +137,8 @@ struct si_cs_shader_state {
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struct si_textures_info {
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struct si_sampler_views views;
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uint64_t depth_texture_mask; /* which textures are depth */
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uint64_t compressed_colortex_mask;
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uint32_t depth_texture_mask; /* which textures are depth */
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uint32_t compressed_colortex_mask;
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};
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struct si_images_info {
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@ -197,10 +197,10 @@ struct si_descriptors {
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unsigned ce_offset;
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/* The i-th bit is set if that element is enabled (non-NULL resource). */
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uint64_t enabled_mask;
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unsigned enabled_mask;
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/* elements of the list that are changed and need to be uploaded */
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uint64_t dirty_mask;
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unsigned dirty_mask;
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/* Whether the CE ram is dirty and needs to be reinitialized entirely
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* before we can do partial updates. */
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