amd: require amdgpu DRM 3.2.0 from April 2016
This removes an early bug workaround. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
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@ -538,6 +538,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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assert(info->drm_major == 3);
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assert(info->drm_major == 3);
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info->is_amdgpu = true;
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info->is_amdgpu = true;
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if (info->drm_minor < 2) {
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fprintf(stderr, "amdgpu: DRM version is %u.%u.%u, but this driver is "
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"only compatible with 3.2.0 (kernel 4.7) or later.\n",
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info->drm_major, info->drm_minor, info->drm_patchlevel);
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return false;
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}
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/* Query hardware and driver information. */
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/* Query hardware and driver information. */
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r = amdgpu_query_gpu_info(dev, amdinfo);
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r = amdgpu_query_gpu_info(dev, amdinfo);
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if (r) {
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if (r) {
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@ -888,8 +895,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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info->has_gpu_reset_status_query = true;
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info->has_gpu_reset_status_query = true;
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info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
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info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
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info->has_format_bc1_through_bc7 = true;
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info->has_format_bc1_through_bc7 = true;
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/* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
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info->kernel_flushes_tc_l2_after_ib = info->gfx_level != GFX8 || info->drm_minor >= 2;
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info->has_indirect_compute_dispatch = true;
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info->has_indirect_compute_dispatch = true;
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/* GFX6 doesn't support unaligned loads. */
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/* GFX6 doesn't support unaligned loads. */
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info->has_unaligned_shader_loads = info->gfx_level != GFX6;
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info->has_unaligned_shader_loads = info->gfx_level != GFX6;
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@ -1500,7 +1505,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
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fprintf(f, " has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
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fprintf(f, " has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
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fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
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fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
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fprintf(f, " has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
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fprintf(f, " has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
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fprintf(f, " kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
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fprintf(f, " has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
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fprintf(f, " has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
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fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
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fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
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fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
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fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
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@ -190,7 +190,6 @@ struct radeon_info {
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bool has_gpu_reset_status_query;
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bool has_gpu_reset_status_query;
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bool has_eqaa_surface_allocator;
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bool has_eqaa_surface_allocator;
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bool has_format_bc1_through_bc7;
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bool has_format_bc1_through_bc7;
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bool kernel_flushes_tc_l2_after_ib;
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bool has_indirect_compute_dispatch;
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bool has_indirect_compute_dispatch;
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bool has_unaligned_shader_loads;
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bool has_unaligned_shader_loads;
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bool has_sparse_vm_mappings;
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bool has_sparse_vm_mappings;
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@ -308,8 +308,8 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
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fprintf(f, "Memory-mapped registers:\n");
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fprintf(f, "Memory-mapped registers:\n");
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si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
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si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
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/* No other registers can be read on DRM < 3.1.0. */
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/* No other registers can be read on radeon. */
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if (!sctx->screen->info.is_amdgpu || sctx->screen->info.drm_minor < 1) {
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if (!sctx->screen->info.is_amdgpu) {
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fprintf(f, "\n");
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fprintf(f, "\n");
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return;
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return;
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}
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}
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@ -55,9 +55,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
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if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39)
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if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39)
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flags |= RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
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flags |= RADEON_FLUSH_START_NEXT_GFX_IB_NOW;
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if (!sscreen->info.kernel_flushes_tc_l2_after_ib) {
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if (ctx->gfx_level == GFX6) {
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wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2;
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} else if (ctx->gfx_level == GFX6) {
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/* The kernel flushes L2 before shaders are finished. */
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/* The kernel flushes L2 before shaders are finished. */
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wait_flags |= wait_ps_cs;
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wait_flags |= wait_ps_cs;
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} else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW) ||
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} else if (!(flags & RADEON_FLUSH_START_NEXT_GFX_IB_NOW) ||
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@ -586,7 +586,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
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ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
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ws->info.has_eqaa_surface_allocator = false;
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ws->info.has_eqaa_surface_allocator = false;
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ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
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ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
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ws->info.kernel_flushes_tc_l2_after_ib = true;
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/* Old kernels disallowed register writes via COPY_DATA
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/* Old kernels disallowed register writes via COPY_DATA
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* that are used for indirect compute dispatches. */
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* that are used for indirect compute dispatches. */
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ws->info.has_indirect_compute_dispatch = ws->info.gfx_level == GFX7 ||
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ws->info.has_indirect_compute_dispatch = ws->info.gfx_level == GFX7 ||
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