parent
bea0c5812b
commit
2e635ef563
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@ -56,6 +56,25 @@ void r300_emit_blend_color_state(struct r300_context* r300,
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}
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}
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void r300_emit_dsa_state(struct r300_context* r300,
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struct r300_dsa_state* dsa)
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{
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struct r300_screen* r300screen =
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(struct r300_screen*)r300->context.screen;
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CS_LOCALS(r300);
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BEGIN_CS(r300screen->caps->is_r500 ? 12 : 10);
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OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
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OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
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OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
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OUT_CS(dsa->z_buffer_control);
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OUT_CS(dsa->z_stencil_control);
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OUT_CS(dsa->stencil_ref_mask);
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OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
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if (r300screen->caps->is_r500) {
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OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
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}
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}
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static void r300_emit_dirty_state(struct r300_context* r300)
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{
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struct r300_screen* r300screen =
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@ -77,17 +96,7 @@ static void r300_emit_dirty_state(struct r300_context* r300)
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}
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if (r300->dirty_state & R300_NEW_DSA) {
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struct r300_dsa_state* dsa = r300->dsa_state;
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OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
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OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
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/* XXX next three are contiguous regs */
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OUT_CS_REG(R300_ZB_CNTL, dsa->z_buffer_control);
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OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control);
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OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask);
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OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
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if (r300screen->caps->is_r500) {
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OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
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}
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r300_emit_dsa_state(r300, r300->dsa_state);
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}
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if (r300->dirty_state & R300_NEW_RASTERIZER) {
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@ -29,3 +29,6 @@ void r300_emit_blend_state(struct r300_context* r300,
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void r300_emit_blend_color_state(struct r300_context* r300,
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struct r300_blend_color_state* bc);
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void r300_emit_dsa_state(struct r300_context* r300,
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struct r300_dsa_state* dsa);
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@ -151,7 +151,6 @@ OUT_CS_REG(0x4BC0, 0x00000002);
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OUT_CS_REG(0x4BC8, 0x00000000);
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OUT_CS_REG(0x4BCC, 0x00000000);
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OUT_CS_REG(0x4BD0, 0x00000000);
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OUT_CS_REG(0x4BD4, 0x00000000);
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OUT_CS_REG(0x4BD8, 0x00000000);
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OUT_CS_REG(0x4BD8, 0x00000000);
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OUT_CS_REG(0x4E00, 0x00000000);
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@ -175,7 +174,6 @@ OUT_CS_REG(0x4F00, 0x00000010);
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OUT_CS_REG(0x4F04, 0x00038038);
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OUT_CS_REG(0x4F08, 0x00FFFF00);
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OUT_CS_REG(0x4F10, 0x00000002);
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OUT_CS_REG(0x4F14, 0x00000001);
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OUT_CS_REG(0x4F18, 0x00000003);
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OUT_CS_REG(0x4F1C, 0x00000000);
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OUT_CS_REG(0x4F28, 0x00000000);
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@ -313,15 +311,14 @@ OUT_CS_REG(0x2208, 0x00F02203);
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OUT_CS_REG(0x2208, 0x00D10021);
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OUT_CS_REG(0x2208, 0x01248021);
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OUT_CS_REG(0x2208, 0x00000000);
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r300_emit_dsa_state(r300, &dsa_clear_state);
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R300_PACIFY;
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OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
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OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
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//OUT_CS_REG(0x4E38, 0x00C00100);
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OUT_CS_REG(0x4E0C, 0x0000000F);
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OUT_CS_REG(0x4F00, 0x00000000);
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OUT_CS_REG(0x4F04, 0x00000000);
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OUT_CS_REG(0x4F08, 0x00FF0000);
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/* XXX Packet3 */
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OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
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OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
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@ -45,4 +45,14 @@ const struct r300_blend_color_state blend_color_clear_state = {
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.blend_color_green_blue = 0x0,
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};
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const struct r300_dsa_state dsa_clear_state = {
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.alpha_function = 0x0,
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.alpha_reference = 0x0,
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.z_buffer_control = 0x0,
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.z_stencil_control = 0x0,
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.stencil_ref_mask = 0x0,
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.z_buffer_top = R300_ZTOP_ENABLE,
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.stencil_ref_bf = 0x0,
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};
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#endif /* R300_SURFACE_H */
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