r600g: properly set non_disp tiling mode for DMA (v2)
Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4409758a04
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2da8ee16a8
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@ -3528,7 +3528,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
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struct r600_texture *rdst = (struct r600_texture*)dst;
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unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
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unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
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unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
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unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
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uint64_t base, addr;
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/* make sure that the dma ring is only one active */
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@ -3541,6 +3541,10 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
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dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
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assert(dst_mode != src_mode);
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/* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
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if (util_format_has_depth(util_format_description(src->format)))
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non_disp_tiling = 1;
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y = 0;
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sub_cmd = 0x8;
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lbpp = util_logbase2(bpp);
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@ -3620,7 +3624,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
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cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
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cs->buf[cs->cdw++] = (slice_tile_max << 0);
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cs->buf[cs->cdw++] = (x << 0) | (z << 18);
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cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25);
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cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28);
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cs->buf[cs->cdw++] = addr & 0xfffffffc;
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cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
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copy_height -= cheight;
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