r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
On cayman, 128bpp surfaces require non_disp ordering for hw access to both linear and tiled surfaces. When we use the 3D engine we can set the non_disp ordering on both the tiled and linear sides (via CB or texture), but when we use the DMA engine, we can only set the non_disp ordering on the tiled side, so after a L2T operation with the DMA engine, the data ends up in the wrong order on the tiled side. v2: cayman/TN only v3: fix comments Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60802 Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3674,6 +3674,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
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return FALSE;
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}
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/* 128 bpp surfaces require non_disp_tiling for both
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* tiled and linear buffers on cayman. However, async
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* DMA only supports it on the tiled side. As such
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* the tile order is backwards after a L2T/T2L packet.
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*/
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if ((rctx->chip_class == CAYMAN) &&
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(src_mode != dst_mode) &&
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(util_format_get_blocksize(src->format) >= 16)) {
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return FALSE;
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}
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if (src_mode == dst_mode) {
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uint64_t dst_offset, src_offset;
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/* simple dma blit would do NOTE code here assume :
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