freedreno/ir3: rename instructions
Turns out this range of opcodes are more general purpose if/else/endif instructions. We should re-work tess to create a basic block and use normal flow control. And possibly (for a6xx+) optimize cases to use if/else/endif when appropriate. Signed-off-by: Rob Clark <robdclark@chromium.org> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
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@ -185,7 +185,7 @@ static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr)
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switch (cat0->opc) {
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case OPC_KILL:
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case OPC_CONDEND:
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case OPC_IF:
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fprintf(ctx->out, " %sp0.%c", cat0->inv ? "!" : "",
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component[cat0->comp]);
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break;
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@ -927,8 +927,9 @@ static const struct opc_info {
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OPC(0, OPC_CHMASK, chmask),
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OPC(0, OPC_CHSH, chsh),
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OPC(0, OPC_FLOW_REV, flow_rev),
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OPC(0, OPC_CONDEND, condend),
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OPC(0, OPC_ENDPATCH, endpatch),
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OPC(0, OPC_IF, if),
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OPC(0, OPC_ELSE, else),
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OPC(0, OPC_ENDIF, endif),
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/* category 1: */
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OPC(1, OPC_MOV, ),
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@ -51,8 +51,9 @@ typedef enum {
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OPC_CHSH = _OPC(0, 10),
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OPC_FLOW_REV = _OPC(0, 11),
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OPC_CONDEND = _OPC(0, 13),
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OPC_ENDPATCH = _OPC(0, 15),
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OPC_IF = _OPC(0, 13),
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OPC_ELSE = _OPC(0, 14),
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OPC_ENDIF = _OPC(0, 15),
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/* category 1: */
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OPC_MOV = _OPC(1, 0),
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@ -148,8 +148,15 @@ static int emit_cat0(struct ir3_instruction *instr, void *ptr,
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cat0->sync = !!(instr->flags & IR3_INSTR_SY);
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cat0->opc_cat = 0;
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if (instr->opc == OPC_CONDEND || instr->opc == OPC_ENDPATCH)
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switch (instr->opc) {
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case OPC_IF:
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case OPC_ELSE:
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case OPC_ENDIF:
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cat0->dummy4 = 16;
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break;
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default:
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break;
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}
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return 0;
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}
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@ -627,7 +627,7 @@ static inline bool is_flow(struct ir3_instruction *instr)
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static inline bool is_kill(struct ir3_instruction *instr)
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{
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return instr->opc == OPC_KILL || instr->opc == OPC_CONDEND;
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return instr->opc == OPC_KILL;
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}
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static inline bool is_nop(struct ir3_instruction *instr)
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@ -1356,8 +1356,9 @@ INSTR1(KILL)
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INSTR0(END)
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INSTR0(CHSH)
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INSTR0(CHMASK)
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INSTR1(CONDEND)
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INSTR0(ENDPATCH)
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INSTR1(IF)
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INSTR0(ELSE)
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INSTR0(ENDIF)
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/* cat2 instructions, most 2 src but some 1 src: */
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INSTR2(ADD_F)
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@ -1423,7 +1423,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_end_patch_ir3:
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assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
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struct ir3_instruction *end = ir3_ENDPATCH(b);
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struct ir3_instruction *end = ir3_ENDIF(b);
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array_insert(b, b->keeps, end);
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end->barrier_class = IR3_BARRIER_EVERYTHING;
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@ -1793,7 +1793,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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/* condition always goes in predicate register: */
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cond->regs[0]->num = regid(REG_P0, 0);
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kill = ir3_CONDEND(b, cond, 0);
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kill = ir3_IF(b, cond, 0);
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kill->barrier_class = IR3_BARRIER_EVERYTHING;
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kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
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@ -139,7 +139,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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regmask_init(&state->needs_sy);
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}
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if (last_n && (last_n->opc == OPC_CONDEND)) {
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if (last_n && (last_n->opc == OPC_IF)) {
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n->flags |= IR3_INSTR_SS;
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regmask_init(&state->needs_ss_war);
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regmask_init(&state->needs_ss);
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@ -531,8 +531,9 @@ emit_tess_epilouge(nir_builder *b, struct state *state)
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nir_intrinsic_set_write_mask(store, (1 << levels[1]->num_components) - 1);
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}
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/* Finally, Insert endpatch instruction, maybe signalling the tess engine
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* that another primitive is ready?
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/* Finally, Insert endpatch instruction:
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*
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* TODO we should re-work this to use normal flow control.
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*/
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nir_intrinsic_instr *end_patch =
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