From 2629cb627c2c4a3f75614886ce0fc0ce76e4f6f1 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 14 Jan 2020 14:46:11 -0800 Subject: [PATCH] freedreno/ir3: rename instructions Turns out this range of opcodes are more general purpose if/else/endif instructions. We should re-work tess to create a basic block and use normal flow control. And possibly (for a6xx+) optimize cases to use if/else/endif when appropriate. Signed-off-by: Rob Clark Tested-by: Marge Bot Part-of: --- src/freedreno/ir3/disasm-a3xx.c | 7 ++++--- src/freedreno/ir3/instr-a3xx.h | 5 +++-- src/freedreno/ir3/ir3.c | 9 ++++++++- src/freedreno/ir3/ir3.h | 7 ++++--- src/freedreno/ir3/ir3_compiler_nir.c | 4 ++-- src/freedreno/ir3/ir3_legalize.c | 2 +- src/freedreno/ir3/ir3_nir_lower_tess.c | 5 +++-- 7 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/freedreno/ir3/disasm-a3xx.c b/src/freedreno/ir3/disasm-a3xx.c index 1cd82876edb..bbc532a46a4 100644 --- a/src/freedreno/ir3/disasm-a3xx.c +++ b/src/freedreno/ir3/disasm-a3xx.c @@ -185,7 +185,7 @@ static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr) switch (cat0->opc) { case OPC_KILL: - case OPC_CONDEND: + case OPC_IF: fprintf(ctx->out, " %sp0.%c", cat0->inv ? "!" : "", component[cat0->comp]); break; @@ -927,8 +927,9 @@ static const struct opc_info { OPC(0, OPC_CHMASK, chmask), OPC(0, OPC_CHSH, chsh), OPC(0, OPC_FLOW_REV, flow_rev), - OPC(0, OPC_CONDEND, condend), - OPC(0, OPC_ENDPATCH, endpatch), + OPC(0, OPC_IF, if), + OPC(0, OPC_ELSE, else), + OPC(0, OPC_ENDIF, endif), /* category 1: */ OPC(1, OPC_MOV, ), diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h index 4a2e9df64f3..b3649f24bdf 100644 --- a/src/freedreno/ir3/instr-a3xx.h +++ b/src/freedreno/ir3/instr-a3xx.h @@ -51,8 +51,9 @@ typedef enum { OPC_CHSH = _OPC(0, 10), OPC_FLOW_REV = _OPC(0, 11), - OPC_CONDEND = _OPC(0, 13), - OPC_ENDPATCH = _OPC(0, 15), + OPC_IF = _OPC(0, 13), + OPC_ELSE = _OPC(0, 14), + OPC_ENDIF = _OPC(0, 15), /* category 1: */ OPC_MOV = _OPC(1, 0), diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c index bcf6a5dd989..18c2936caa7 100644 --- a/src/freedreno/ir3/ir3.c +++ b/src/freedreno/ir3/ir3.c @@ -148,8 +148,15 @@ static int emit_cat0(struct ir3_instruction *instr, void *ptr, cat0->sync = !!(instr->flags & IR3_INSTR_SY); cat0->opc_cat = 0; - if (instr->opc == OPC_CONDEND || instr->opc == OPC_ENDPATCH) + switch (instr->opc) { + case OPC_IF: + case OPC_ELSE: + case OPC_ENDIF: cat0->dummy4 = 16; + break; + default: + break; + } return 0; } diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 70d7d5e9cb3..e777bf440e6 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -627,7 +627,7 @@ static inline bool is_flow(struct ir3_instruction *instr) static inline bool is_kill(struct ir3_instruction *instr) { - return instr->opc == OPC_KILL || instr->opc == OPC_CONDEND; + return instr->opc == OPC_KILL; } static inline bool is_nop(struct ir3_instruction *instr) @@ -1356,8 +1356,9 @@ INSTR1(KILL) INSTR0(END) INSTR0(CHSH) INSTR0(CHMASK) -INSTR1(CONDEND) -INSTR0(ENDPATCH) +INSTR1(IF) +INSTR0(ELSE) +INSTR0(ENDIF) /* cat2 instructions, most 2 src but some 1 src: */ INSTR2(ADD_F) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 7a26a57c08d..698d98c6c6a 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1423,7 +1423,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_end_patch_ir3: assert(ctx->so->type == MESA_SHADER_TESS_CTRL); - struct ir3_instruction *end = ir3_ENDPATCH(b); + struct ir3_instruction *end = ir3_ENDIF(b); array_insert(b, b->keeps, end); end->barrier_class = IR3_BARRIER_EVERYTHING; @@ -1793,7 +1793,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* condition always goes in predicate register: */ cond->regs[0]->num = regid(REG_P0, 0); - kill = ir3_CONDEND(b, cond, 0); + kill = ir3_IF(b, cond, 0); kill->barrier_class = IR3_BARRIER_EVERYTHING; kill->barrier_conflict = IR3_BARRIER_EVERYTHING; diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index 025a8537c18..1920fcfb93a 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -139,7 +139,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) regmask_init(&state->needs_sy); } - if (last_n && (last_n->opc == OPC_CONDEND)) { + if (last_n && (last_n->opc == OPC_IF)) { n->flags |= IR3_INSTR_SS; regmask_init(&state->needs_ss_war); regmask_init(&state->needs_ss); diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c index 056b009ef75..873e3b607a0 100644 --- a/src/freedreno/ir3/ir3_nir_lower_tess.c +++ b/src/freedreno/ir3/ir3_nir_lower_tess.c @@ -531,8 +531,9 @@ emit_tess_epilouge(nir_builder *b, struct state *state) nir_intrinsic_set_write_mask(store, (1 << levels[1]->num_components) - 1); } - /* Finally, Insert endpatch instruction, maybe signalling the tess engine - * that another primitive is ready? + /* Finally, Insert endpatch instruction: + * + * TODO we should re-work this to use normal flow control. */ nir_intrinsic_instr *end_patch =