intel/compiler: Implement Mesh Output
Use the same URB access helpers that were added for Task Output. The Arrayed I/O (per-primitive and per-vertex) is handled by applying the pitch from the MUE layout into the NIR intrinsics and including the non-arrayed offset on top of it. After that, the index src can be used directly for lowering. Because we keep around the non-arrayed offset AND the pitch is aligned, we can identify cases where the access is indirect but guaranteed to be aligned, and dispatch a single message. Added a TODO to explore that later. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13661>
This commit is contained in:
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70ace2bbcd
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1f438eb033
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@ -1850,6 +1850,10 @@ fs_visitor::assign_curb_setup()
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void
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brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data)
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{
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/* TODO(mesh): Review usage of this in the context of Mesh, we may want to
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* skip per-primitive attributes here.
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*/
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/* Make sure uint8_t is sufficient */
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STATIC_ASSERT(VARYING_SLOT_MAX <= 0xff);
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uint8_t index = 0;
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@ -224,6 +224,261 @@ brw_nir_lower_tue_inputs(nir_shader *nir, const brw_tue_map *map)
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nir_lower_io_lower_64bit_to_32);
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}
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/* Mesh URB Entry consists of an initial section
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*
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* - Primitive Count
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* - Primitive Indices (from 0 to Max-1)
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* - Padding to 32B if needed
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*
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* optionally followed by a section for per-primitive data,
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* in which each primitive (from 0 to Max-1) gets
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*
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* - Primitive Header (e.g. ViewportIndex)
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* - Primitive Custom Attributes
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*
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* then followed by a section for per-vertex data
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*
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* - Vertex Header (e.g. Position)
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* - Vertex Custom Attributes
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*
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* Each per-element section has a pitch and a starting offset. All the
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* individual attributes offsets in start_dw are considering the first entry
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* of the section (i.e. where the Position for first vertex, or ViewportIndex
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* for first primitive). Attributes for other elements are calculated using
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* the pitch.
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*/
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static void
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brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map)
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{
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memset(map, 0, sizeof(*map));
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for (int i = 0; i < VARYING_SLOT_MAX; i++)
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map->start_dw[i] = -1;
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unsigned vertices_per_primitive = 0;
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switch (nir->info.mesh.primitive_type) {
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case GL_POINTS:
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vertices_per_primitive = 1;
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break;
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case GL_LINES:
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vertices_per_primitive = 2;
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break;
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case GL_TRIANGLES:
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vertices_per_primitive = 3;
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break;
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default:
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unreachable("invalid primitive type");
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}
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map->max_primitives = nir->info.mesh.max_primitives_out;
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map->max_vertices = nir->info.mesh.max_vertices_out;
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uint64_t outputs_written = nir->info.outputs_written;
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/* Assign initial section. */
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if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) & outputs_written) {
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map->start_dw[VARYING_SLOT_PRIMITIVE_COUNT] = 0;
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outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT);
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}
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if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) & outputs_written) {
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map->start_dw[VARYING_SLOT_PRIMITIVE_INDICES] = 1;
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outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES);
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}
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/* One dword for primitives count then K extra dwords for each
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* primitive. Note this should change when we implement other index types.
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*/
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const unsigned primitive_list_size_dw = 1 + vertices_per_primitive * map->max_primitives;
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/* TODO(mesh): Multiview. */
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map->per_primitive_header_size_dw = 0;
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map->per_primitive_start_dw = ALIGN(primitive_list_size_dw, 8);
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unsigned next_primitive = map->per_primitive_start_dw +
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map->per_primitive_header_size_dw;
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u_foreach_bit64(location, outputs_written & nir->info.per_primitive_outputs) {
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assert(map->start_dw[location] == -1);
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assert(location >= VARYING_SLOT_VAR0);
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map->start_dw[location] = next_primitive;
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next_primitive += 4;
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}
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map->per_primitive_data_size_dw = next_primitive -
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map->per_primitive_start_dw -
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map->per_primitive_header_size_dw;
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map->per_primitive_pitch_dw = ALIGN(map->per_primitive_header_size_dw +
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map->per_primitive_data_size_dw, 8);
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/* TODO(mesh): Multiview. */
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map->per_vertex_header_size_dw = 8;
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map->per_vertex_start_dw = ALIGN(map->per_primitive_start_dw +
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map->per_primitive_pitch_dw * map->max_primitives, 8);
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unsigned next_vertex = map->per_vertex_start_dw +
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map->per_vertex_header_size_dw;
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u_foreach_bit64(location, outputs_written & ~nir->info.per_primitive_outputs) {
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assert(map->start_dw[location] == -1);
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unsigned start;
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switch (location) {
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case VARYING_SLOT_PSIZ:
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start = map->per_vertex_start_dw + 3;
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break;
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case VARYING_SLOT_POS:
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start = map->per_vertex_start_dw + 4;
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break;
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default:
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assert(location >= VARYING_SLOT_VAR0);
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start = next_vertex;
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next_vertex += 4;
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break;
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}
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map->start_dw[location] = start;
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}
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map->per_vertex_data_size_dw = next_vertex -
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map->per_vertex_start_dw -
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map->per_vertex_header_size_dw;
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map->per_vertex_pitch_dw = ALIGN(map->per_vertex_header_size_dw +
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map->per_vertex_data_size_dw, 8);
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map->size_dw =
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map->per_vertex_start_dw + map->per_vertex_pitch_dw * map->max_vertices;
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assert(map->size_dw % 8 == 0);
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}
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static void
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brw_print_mue_map(FILE *fp, const struct brw_mue_map *map)
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{
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fprintf(fp, "MUE map (%d dwords, %d primitives, %d vertices)\n",
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map->size_dw, map->max_primitives, map->max_vertices);
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fprintf(fp, " %4d: VARYING_SLOT_PRIMITIVE_COUNT\n",
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map->start_dw[VARYING_SLOT_PRIMITIVE_COUNT]);
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fprintf(fp, " %4d: VARYING_SLOT_PRIMITIVE_INDICES\n",
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map->start_dw[VARYING_SLOT_PRIMITIVE_INDICES]);
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fprintf(fp, " ----- per primitive (start %d, header_size %d, data_size %d, pitch %d)\n",
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map->per_primitive_start_dw,
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map->per_primitive_header_size_dw,
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map->per_primitive_data_size_dw,
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map->per_primitive_pitch_dw);
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for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) {
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if (map->start_dw[i] < 0)
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continue;
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const unsigned offset = map->start_dw[i];
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if (offset >= map->per_primitive_start_dw &&
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offset < map->per_primitive_start_dw + map->per_primitive_pitch_dw) {
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fprintf(fp, " %4d: %s\n", offset,
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gl_varying_slot_name_for_stage((gl_varying_slot)i,
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MESA_SHADER_MESH));
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}
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}
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fprintf(fp, " ----- per vertex (start %d, header_size %d, data_size %d, pitch %d)\n",
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map->per_vertex_start_dw,
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map->per_vertex_header_size_dw,
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map->per_vertex_data_size_dw,
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map->per_vertex_pitch_dw);
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for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) {
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if (map->start_dw[i] < 0)
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continue;
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const unsigned offset = map->start_dw[i];
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if (offset >= map->per_vertex_start_dw &&
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offset < map->per_vertex_start_dw + map->per_vertex_pitch_dw) {
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fprintf(fp, " %4d: %s\n", offset,
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gl_varying_slot_name_for_stage((gl_varying_slot)i,
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MESA_SHADER_MESH));
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}
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}
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fprintf(fp, "\n");
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}
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static void
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brw_nir_lower_mue_outputs(nir_shader *nir, const struct brw_mue_map *map)
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{
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nir_foreach_shader_out_variable(var, nir) {
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int location = var->data.location;
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assert(location >= 0);
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assert(map->start_dw[location] != -1);
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var->data.driver_location = map->start_dw[location];
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}
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nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
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nir_lower_io_lower_64bit_to_32);
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}
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static void
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brw_nir_adjust_offset_for_arrayed_indices(nir_shader *nir, const struct brw_mue_map *map)
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{
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/* TODO(mesh): Check if we need to inject extra vertex header / primitive
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* setup. If so, we should add them together some required value for
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* vertex/primitive.
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*/
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/* Remap per_vertex and per_primitive offsets using the extra source and the pitch. */
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nir_foreach_function(function, nir) {
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if (function->impl) {
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nir_builder b;
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nir_builder_init(&b, function->impl);
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nir_foreach_block(block, function->impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_store_per_vertex_output: {
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const bool is_load = intrin->intrinsic == nir_intrinsic_load_per_vertex_output;
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nir_src *index_src = &intrin->src[is_load ? 0 : 1];
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nir_src *offset_src = &intrin->src[is_load ? 1 : 2];
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assert(index_src->is_ssa);
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b.cursor = nir_before_instr(&intrin->instr);
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nir_ssa_def *offset =
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nir_iadd(&b,
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offset_src->ssa,
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nir_imul_imm(&b, index_src->ssa, map->per_vertex_pitch_dw));
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nir_instr_rewrite_src(&intrin->instr, offset_src, nir_src_for_ssa(offset));
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break;
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}
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case nir_intrinsic_load_per_primitive_output:
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case nir_intrinsic_store_per_primitive_output: {
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const bool is_load = intrin->intrinsic == nir_intrinsic_load_per_primitive_output;
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nir_src *index_src = &intrin->src[is_load ? 0 : 1];
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nir_src *offset_src = &intrin->src[is_load ? 1 : 2];
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assert(index_src->is_ssa);
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b.cursor = nir_before_instr(&intrin->instr);
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assert(index_src->is_ssa);
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nir_ssa_def *offset =
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nir_iadd(&b,
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offset_src->ssa,
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nir_imul_imm(&b, index_src->ssa, map->per_primitive_pitch_dw));
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nir_instr_rewrite_src(&intrin->instr, offset_src, nir_src_for_ssa(offset));
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break;
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}
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default:
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/* Nothing to do. */
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break;
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}
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}
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}
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nir_metadata_preserve(function->impl, nir_metadata_none);
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}
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}
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}
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const unsigned *
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brw_compile_mesh(const struct brw_compiler *compiler,
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void *mem_ctx,
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/* TODO(mesh): Use other index formats (that are more compact) for optimization. */
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prog_data->index_format = BRW_INDEX_FORMAT_U32;
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brw_compute_mue_map(nir, &prog_data->map);
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const unsigned required_dispatch_width =
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brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
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brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
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NIR_PASS_V(shader, brw_nir_lower_tue_inputs, params->tue_map);
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NIR_PASS_V(shader, brw_nir_lower_mue_outputs, &prog_data->map);
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NIR_PASS_V(shader, brw_nir_adjust_offset_for_arrayed_indices, &prog_data->map);
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NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
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brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
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@ -300,6 +559,8 @@ brw_compile_mesh(const struct brw_compiler *compiler,
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fprintf(stderr, "Mesh Input ");
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brw_print_tue_map(stderr, params->tue_map);
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}
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fprintf(stderr, "Mesh Output ");
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brw_print_mue_map(stderr, &prog_data->map);
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}
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fs_generator g(compiler, params->log_data, mem_ctx,
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@ -590,6 +851,11 @@ fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *ins
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fs_reg src = get_nir_src(instr->src[0]);
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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/* TODO(mesh): for per_vertex and per_primitive, if we could keep around
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* the non-array-index offset, we could use to decide if we can perform
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* either one or (at most) two writes instead one per component.
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*/
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if (nir_src_is_const(*offset_nir_src))
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emit_urb_direct_writes(bld, instr, src);
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else
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@ -602,6 +868,11 @@ fs_visitor::emit_task_mesh_load(const fs_builder &bld, nir_intrinsic_instr *inst
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fs_reg dest = get_nir_dest(instr->dest);
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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/* TODO(mesh): for per_vertex and per_primitive, if we could keep around
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* the non-array-index offset, we could use to decide if we can perform
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* a single large aligned read instead one per component.
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*/
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if (nir_src_is_const(*offset_nir_src))
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emit_urb_direct_reads(bld, instr, dest);
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else
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@ -639,13 +910,13 @@ fs_visitor::nir_emit_mesh_intrinsic(const fs_builder &bld,
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case nir_intrinsic_store_per_primitive_output:
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case nir_intrinsic_store_per_vertex_output:
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case nir_intrinsic_store_output:
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_load_per_primitive_output:
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case nir_intrinsic_load_output:
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/* TODO(mesh): Mesh Output. */
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emit_task_mesh_store(bld, instr);
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break;
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case nir_intrinsic_load_input:
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_load_per_primitive_output:
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case nir_intrinsic_load_output:
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emit_task_mesh_load(bld, instr);
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break;
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@ -153,7 +153,8 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
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}
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if (is_scalar && stage != MESA_SHADER_TESS_CTRL &&
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stage != MESA_SHADER_TASK)
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stage != MESA_SHADER_TASK &&
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stage != MESA_SHADER_MESH)
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indirect_mask |= nir_var_shader_out;
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/* On HSW+, we allow indirects in scalar shaders. They get implemented
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