intel/compiler: Implement Task Output and Mesh Input
Implement the output written by the task *workgroup* and available to all the mesh *workgroups* dispatched from that task. We currently ignore any layout annotations (since they are not really testable) and produce a (packed) layout ourselves. The URB messages are only SIMD8, so for larger SIMDs, the functions will produce multiple messages. Making this lowering here instead of the generic lower_simd_width() since it is not just a matter of zip/unzip, e.g. the offset must be adjusted. Indirect writes/reads are implemented by handling one component at a time and using the PER_SLOT variant of the messages. Note that VK_NV_mesh_shader allows reading outputs, so add support for that as well. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13661>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
171bdd2ec6
commit
70ace2bbcd
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@ -329,6 +329,11 @@ public:
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void emit_cs_terminate();
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fs_reg *emit_work_group_id_setup();
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void emit_task_mesh_store(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void emit_task_mesh_load(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void emit_barrier();
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void emit_shader_time_begin();
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@ -30,6 +30,90 @@
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using namespace brw;
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static inline int
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type_size_scalar_dwords(const struct glsl_type *type, bool bindless)
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{
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return glsl_count_dword_slots(type, bindless);
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}
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static void
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brw_nir_lower_tue_outputs(nir_shader *nir, const brw_tue_map *map)
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{
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nir_foreach_shader_out_variable(var, nir) {
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int location = var->data.location;
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assert(location >= 0);
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assert(map->start_dw[location] != -1);
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var->data.driver_location = map->start_dw[location];
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}
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nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords,
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nir_lower_io_lower_64bit_to_32);
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}
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static void
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brw_compute_tue_map(struct nir_shader *nir, struct brw_tue_map *map)
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{
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memset(map, 0, sizeof(*map));
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map->start_dw[VARYING_SLOT_TASK_COUNT] = 0;
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/* Words 1-3 are used for "Dispatch Dimensions" feature, to allow mapping a
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* 3D dispatch into the 1D dispatch supported by HW. So ignore those.
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*/
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/* From bspec: "It is suggested that SW reserve the 16 bytes following the
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* TUE Header, and therefore start the SW-defined data structure at 32B
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* alignment. This allows the TUE Header to always be written as 32 bytes
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* with 32B alignment, the most optimal write performance case."
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*/
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map->per_task_data_start_dw = 8;
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/* Compact the data: find the size associated with each location... */
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nir_foreach_shader_out_variable(var, nir) {
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const int location = var->data.location;
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if (location == VARYING_SLOT_TASK_COUNT)
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continue;
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assert(location >= VARYING_SLOT_VAR0);
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assert(location < VARYING_SLOT_MAX);
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map->start_dw[location] += type_size_scalar_dwords(var->type, false);
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}
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/* ...then assign positions using those sizes. */
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unsigned next = map->per_task_data_start_dw;
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for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) {
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if (i == VARYING_SLOT_TASK_COUNT)
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continue;
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if (map->start_dw[i] == 0) {
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map->start_dw[i] = -1;
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} else {
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const unsigned size = map->start_dw[i];
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map->start_dw[i] = next;
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next += size;
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}
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}
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map->size_dw = ALIGN(next, 8);
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}
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static void
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brw_print_tue_map(FILE *fp, const struct brw_tue_map *map)
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{
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fprintf(fp, "TUE map (%d dwords)\n", map->size_dw);
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fprintf(fp, " %4d: VARYING_SLOT_TASK_COUNT\n",
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map->start_dw[VARYING_SLOT_TASK_COUNT]);
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for (int i = VARYING_SLOT_VAR0; i < VARYING_SLOT_MAX; i++) {
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if (map->start_dw[i] != -1) {
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fprintf(fp, " %4d: VARYING_SLOT_VAR%d\n", map->start_dw[i],
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i - VARYING_SLOT_VAR0);
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}
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}
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fprintf(fp, "\n");
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}
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const unsigned *
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brw_compile_task(const struct brw_compiler *compiler,
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void *mem_ctx,
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@ -47,6 +131,8 @@ brw_compile_task(const struct brw_compiler *compiler,
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prog_data->base.local_size[1] = nir->info.workgroup_size[1];
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prog_data->base.local_size[2] = nir->info.workgroup_size[2];
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brw_compute_tue_map(nir, &prog_data->map);
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const unsigned required_dispatch_width =
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brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
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@ -63,6 +149,7 @@ brw_compile_task(const struct brw_compiler *compiler,
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nir_shader *shader = nir_shader_clone(mem_ctx, nir);
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brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
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NIR_PASS_V(shader, brw_nir_lower_tue_outputs, &prog_data->map);
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NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
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brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
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@ -95,6 +182,11 @@ brw_compile_task(const struct brw_compiler *compiler,
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fs_visitor *selected = v[selected_simd];
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prog_data->base.prog_mask = 1 << selected_simd;
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if (unlikely(debug_enabled)) {
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fprintf(stderr, "Task Output ");
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brw_print_tue_map(stderr, &prog_data->map);
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}
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fs_generator g(compiler, params->log_data, mem_ctx,
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&prog_data->base.base, false, MESA_SHADER_TASK);
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if (unlikely(debug_enabled)) {
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@ -115,6 +207,23 @@ brw_compile_task(const struct brw_compiler *compiler,
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return g.get_assembly();
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}
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static void
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brw_nir_lower_tue_inputs(nir_shader *nir, const brw_tue_map *map)
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{
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if (!map)
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return;
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nir_foreach_shader_in_variable(var, nir) {
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int location = var->data.location;
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assert(location >= 0);
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assert(map->start_dw[location] != -1);
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var->data.driver_location = map->start_dw[location];
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}
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nir_lower_io(nir, nir_var_shader_in, type_size_scalar_dwords,
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nir_lower_io_lower_64bit_to_32);
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}
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const unsigned *
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brw_compile_mesh(const struct brw_compiler *compiler,
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void *mem_ctx,
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@ -153,6 +262,7 @@ brw_compile_mesh(const struct brw_compiler *compiler,
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nir_shader *shader = nir_shader_clone(mem_ctx, nir);
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brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true /* is_scalar */);
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NIR_PASS_V(shader, brw_nir_lower_tue_inputs, params->tue_map);
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NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);
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brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
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@ -185,6 +295,13 @@ brw_compile_mesh(const struct brw_compiler *compiler,
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fs_visitor *selected = v[selected_simd];
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prog_data->base.prog_mask = 1 << selected_simd;
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if (unlikely(debug_enabled)) {
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if (params->tue_map) {
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fprintf(stderr, "Mesh Input ");
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brw_print_tue_map(stderr, params->tue_map);
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}
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}
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fs_generator g(compiler, params->log_data, mem_ctx,
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&prog_data->base.base, false, MESA_SHADER_MESH);
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if (unlikely(debug_enabled)) {
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@ -205,6 +322,292 @@ brw_compile_mesh(const struct brw_compiler *compiler,
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return g.get_assembly();
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}
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static fs_reg
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get_mesh_urb_handle(const fs_builder &bld, nir_intrinsic_op op)
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{
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const unsigned subreg = op == nir_intrinsic_load_input ? 7 : 6;
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fs_builder ubld8 = bld.group(8, 0).exec_all();
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fs_reg h = ubld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
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ubld8.MOV(h, retype(brw_vec1_grf(0, subreg), BRW_REGISTER_TYPE_UD));
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ubld8.AND(h, h, brw_imm_ud(0xFFFF));
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return h;
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}
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static void
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emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &src)
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{
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assert(nir_src_bit_size(instr->src[0]) == 32);
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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assert(nir_src_is_const(*offset_nir_src));
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fs_reg urb_handle = get_mesh_urb_handle(bld, instr->intrinsic);
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 4);
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const unsigned mask = nir_intrinsic_write_mask(instr);
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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nir_src_as_uint(*offset_nir_src) +
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nir_intrinsic_component(instr);
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/* URB writes are vec4 aligned but the intrinsic offsets are in dwords.
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* With a max of 4 components, an intrinsic can require up to two writes.
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*
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* First URB write will be shifted by comp_shift. If there are other
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* components left, then dispatch a second write. In addition to that,
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* take mask into account to decide whether each write will be actually
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* needed.
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*/
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const unsigned comp_shift = offset_in_dwords % 4;
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const unsigned first_comps = MIN2(comps, 4 - comp_shift);
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const unsigned second_comps = comps - first_comps;
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const unsigned first_mask = (mask << comp_shift) & 0xF;
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const unsigned second_mask = (mask >> (4 - comp_shift)) & 0xF;
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if (first_mask > 0) {
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for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) {
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fs_builder bld8 = bld.group(8, q);
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fs_reg payload_srcs[6];
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unsigned p = 0;
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payload_srcs[p++] = urb_handle;
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payload_srcs[p++] = brw_imm_ud(first_mask << 16);
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const unsigned header_size = p;
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for (unsigned i = 0; i < comp_shift; i++)
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payload_srcs[p++] = reg_undef;
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for (unsigned c = 0; c < first_comps; c++)
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payload_srcs[p++] = quarter(offset(src, bld, c), q);
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fs_reg payload = bld8.vgrf(BRW_REGISTER_TYPE_UD, p);
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bld8.LOAD_PAYLOAD(payload, payload_srcs, p, header_size);
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fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, reg_undef, payload);
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inst->mlen = p;
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inst->offset = offset_in_dwords / 4;
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}
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}
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if (second_mask > 0) {
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for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) {
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fs_builder bld8 = bld.group(8, q);
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fs_reg payload_srcs[6];
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unsigned p = 0;
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payload_srcs[p++] = urb_handle;
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payload_srcs[p++] = brw_imm_ud(second_mask << 16);
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const unsigned header_size = p;
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for (unsigned c = 0; c < second_comps; c++)
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payload_srcs[p++] = quarter(offset(src, bld, c + first_comps), q);
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fs_reg payload = bld8.vgrf(BRW_REGISTER_TYPE_UD, p);
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bld8.LOAD_PAYLOAD(payload, payload_srcs, p, header_size);
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fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, reg_undef, payload);
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inst->mlen = p;
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inst->offset = (offset_in_dwords / 4) + 1;
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}
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}
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}
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static void
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emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &src, const fs_reg &offset_src)
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{
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assert(nir_src_bit_size(instr->src[0]) == 32);
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 4);
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fs_reg urb_handle = get_mesh_urb_handle(bld, instr->intrinsic);
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const unsigned base_in_dwords = nir_intrinsic_base(instr) +
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nir_intrinsic_component(instr);
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/* Use URB write message that allow different offsets per-slot. The offset
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* is in units of vec4s (128 bits), so we use a write for each component,
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* replicating it in the sources and applying the appropriate mask based on
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* the dword offset.
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*/
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for (unsigned c = 0; c < comps; c++) {
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if (((1 << c) & nir_intrinsic_write_mask(instr)) == 0)
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continue;
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fs_reg src_comp = offset(src, bld, c);
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for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) {
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fs_builder bld8 = bld.group(8, q);
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fs_reg off = bld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
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bld8.MOV(off, quarter(offset_src, q));
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bld8.ADD(off, off, brw_imm_ud(c + base_in_dwords));
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fs_reg mask = bld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
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bld8.AND(mask, off, brw_imm_ud(0x3));
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fs_reg one = bld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
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bld8.MOV(one, brw_imm_ud(1));
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bld8.SHL(mask, one, mask);
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bld8.SHL(mask, mask, brw_imm_ud(16));
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bld8.SHR(off, off, brw_imm_ud(2));
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fs_reg payload_srcs[7];
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int x = 0;
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payload_srcs[x++] = urb_handle;
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payload_srcs[x++] = off;
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payload_srcs[x++] = mask;
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for (unsigned j = 0; j < 4; j++)
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payload_srcs[x++] = quarter(src_comp, q);
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fs_reg payload = bld8.vgrf(BRW_REGISTER_TYPE_UD, x);
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bld8.LOAD_PAYLOAD(payload, payload_srcs, x, 3);
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fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, reg_undef, payload);
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inst->mlen = x;
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inst->offset = 0;
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}
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}
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}
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static void
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emit_urb_direct_reads(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &dest)
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{
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assert(nir_dest_bit_size(instr->dest) == 32);
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unsigned comps = nir_dest_num_components(instr->dest);
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if (comps == 0)
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return;
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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assert(nir_src_is_const(*offset_nir_src));
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fs_reg urb_handle = get_mesh_urb_handle(bld, instr->intrinsic);
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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nir_src_as_uint(*offset_nir_src) +
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nir_intrinsic_component(instr);
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const unsigned comp_offset = offset_in_dwords % 4;
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const unsigned num_regs = comp_offset + comps;
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fs_builder ubld8 = bld.group(8, 0).exec_all();
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fs_reg data = ubld8.vgrf(BRW_REGISTER_TYPE_UD, num_regs);
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fs_inst *inst = ubld8.emit(SHADER_OPCODE_URB_READ_SIMD8, data, urb_handle);
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inst->mlen = 1;
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inst->offset = offset_in_dwords / 4;
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inst->size_written = num_regs * REG_SIZE;
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for (unsigned c = 0; c < comps; c++) {
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fs_reg dest_comp = offset(dest, bld, c);
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fs_reg data_comp = horiz_stride(offset(data, ubld8, comp_offset + c), 0);
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bld.MOV(retype(dest_comp, BRW_REGISTER_TYPE_UD), data_comp);
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}
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}
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static void
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emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &dest, const fs_reg &offset_src)
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{
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assert(nir_dest_bit_size(instr->dest) == 32);
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unsigned comps = nir_dest_num_components(instr->dest);
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if (comps == 0)
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return;
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fs_reg seq_ud;
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{
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fs_builder ubld8 = bld.group(8, 0).exec_all();
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seq_ud = ubld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
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fs_reg seq_uw = ubld8.vgrf(BRW_REGISTER_TYPE_UW, 1);
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ubld8.MOV(seq_uw, fs_reg(brw_imm_v(0x76543210)));
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ubld8.MOV(seq_ud, seq_uw);
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ubld8.SHL(seq_ud, seq_ud, brw_imm_ud(2));
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}
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fs_reg urb_handle = get_mesh_urb_handle(bld, instr->intrinsic);
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const unsigned base_in_dwords = nir_intrinsic_base(instr) +
|
||||
nir_intrinsic_component(instr);
|
||||
|
||||
for (unsigned c = 0; c < comps; c++) {
|
||||
for (unsigned q = 0; q < bld.dispatch_width() / 8; q++) {
|
||||
fs_builder bld8 = bld.group(8, q);
|
||||
|
||||
fs_reg off = bld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
|
||||
bld8.MOV(off, quarter(offset_src, q));
|
||||
bld8.ADD(off, off, brw_imm_ud(base_in_dwords + c));
|
||||
|
||||
STATIC_ASSERT(util_is_power_of_two_nonzero(REG_SIZE) && REG_SIZE > 1);
|
||||
|
||||
fs_reg comp = bld8.vgrf(BRW_REGISTER_TYPE_UD, 1);
|
||||
bld8.AND(comp, off, brw_imm_ud(0x3));
|
||||
bld8.SHL(comp, comp, brw_imm_ud(ffs(REG_SIZE) - 1));
|
||||
bld8.ADD(comp, comp, seq_ud);
|
||||
|
||||
bld8.SHR(off, off, brw_imm_ud(2));
|
||||
|
||||
fs_reg payload_srcs[2];
|
||||
payload_srcs[0] = urb_handle;
|
||||
payload_srcs[1] = off;
|
||||
|
||||
fs_reg payload = bld8.vgrf(BRW_REGISTER_TYPE_UD, 2);
|
||||
bld8.LOAD_PAYLOAD(payload, payload_srcs, 2, 2);
|
||||
|
||||
fs_reg data = bld8.vgrf(BRW_REGISTER_TYPE_UD, 4);
|
||||
|
||||
fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, data, payload);
|
||||
inst->mlen = 2;
|
||||
inst->offset = 0;
|
||||
inst->size_written = 4 * REG_SIZE;
|
||||
|
||||
fs_reg dest_comp = offset(dest, bld, c);
|
||||
bld8.emit(SHADER_OPCODE_MOV_INDIRECT,
|
||||
retype(quarter(dest_comp, q), BRW_REGISTER_TYPE_UD),
|
||||
data,
|
||||
comp,
|
||||
brw_imm_ud(4));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *instr)
|
||||
{
|
||||
fs_reg src = get_nir_src(instr->src[0]);
|
||||
nir_src *offset_nir_src = nir_get_io_offset_src(instr);
|
||||
|
||||
if (nir_src_is_const(*offset_nir_src))
|
||||
emit_urb_direct_writes(bld, instr, src);
|
||||
else
|
||||
emit_urb_indirect_writes(bld, instr, src, get_nir_src(*offset_nir_src));
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::emit_task_mesh_load(const fs_builder &bld, nir_intrinsic_instr *instr)
|
||||
{
|
||||
fs_reg dest = get_nir_dest(instr->dest);
|
||||
nir_src *offset_nir_src = nir_get_io_offset_src(instr);
|
||||
|
||||
if (nir_src_is_const(*offset_nir_src))
|
||||
emit_urb_direct_reads(bld, instr, dest);
|
||||
else
|
||||
emit_urb_indirect_reads(bld, instr, dest, get_nir_src(*offset_nir_src));
|
||||
}
|
||||
|
||||
void
|
||||
fs_visitor::nir_emit_task_intrinsic(const fs_builder &bld,
|
||||
nir_intrinsic_instr *instr)
|
||||
|
|
@ -213,8 +616,11 @@ fs_visitor::nir_emit_task_intrinsic(const fs_builder &bld,
|
|||
|
||||
switch (instr->intrinsic) {
|
||||
case nir_intrinsic_store_output:
|
||||
emit_task_mesh_store(bld, instr);
|
||||
break;
|
||||
|
||||
case nir_intrinsic_load_output:
|
||||
/* TODO(mesh): Task Output. */
|
||||
emit_task_mesh_load(bld, instr);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -230,10 +636,6 @@ fs_visitor::nir_emit_mesh_intrinsic(const fs_builder &bld,
|
|||
assert(stage == MESA_SHADER_MESH);
|
||||
|
||||
switch (instr->intrinsic) {
|
||||
case nir_intrinsic_load_input:
|
||||
/* TODO(mesh): Mesh Input. */
|
||||
break;
|
||||
|
||||
case nir_intrinsic_store_per_primitive_output:
|
||||
case nir_intrinsic_store_per_vertex_output:
|
||||
case nir_intrinsic_store_output:
|
||||
|
|
@ -243,6 +645,10 @@ fs_visitor::nir_emit_mesh_intrinsic(const fs_builder &bld,
|
|||
/* TODO(mesh): Mesh Output. */
|
||||
break;
|
||||
|
||||
case nir_intrinsic_load_input:
|
||||
emit_task_mesh_load(bld, instr);
|
||||
break;
|
||||
|
||||
default:
|
||||
nir_emit_task_mesh_intrinsic(bld, instr);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -152,7 +152,8 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
|
|||
break;
|
||||
}
|
||||
|
||||
if (is_scalar && stage != MESA_SHADER_TESS_CTRL)
|
||||
if (is_scalar && stage != MESA_SHADER_TESS_CTRL &&
|
||||
stage != MESA_SHADER_TASK)
|
||||
indirect_mask |= nir_var_shader_out;
|
||||
|
||||
/* On HSW+, we allow indirects in scalar shaders. They get implemented
|
||||
|
|
|
|||
Loading…
Reference in New Issue