intel/blorp: Only double the fast-clear rect alignment on HSW
This restriction was accidentally added to the BSpec/PRM as an unrestricted restriction starting with the HSW docs and it was never removed. However, it only ever applied to HSW and actually potentially causes problems on BDW and above where we have mipmapped fast-clears. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
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@ -259,16 +259,21 @@ get_fast_clear_rect(const struct isl_device *dev,
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x_scaledown = x_align / 2;
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y_scaledown = y_align / 2;
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/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
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* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
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* Clear of Non-MultiSampled Render Target Restrictions":
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*
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* Clear rectangle must be aligned to two times the number of
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* pixels in the table shown below due to 16x16 hashing across the
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* slice.
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*/
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x_align *= 2;
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y_align *= 2;
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if (ISL_DEV_IS_HASWELL(dev)) {
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/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
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* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
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* Clear of Non-MultiSampled Render Target Restrictions":
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*
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* Clear rectangle must be aligned to two times the number of
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* pixels in the table shown below due to 16x16 hashing across the
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* slice.
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*
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* This restriction is only documented to exist on HSW GT3 but
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* empirical evidence suggests that it's also needed GT2.
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*/
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x_align *= 2;
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y_align *= 2;
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}
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} else {
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assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);
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