freedreno/a6xx: re-arrange program stageobj/group
Split out a separate program config state group to run early before the other groups. This seems to help w/ intermittent "missed tiles" (although I had assumed that was a mem2gmem issue), or at least I can't reproduce that issue with this patch, but can without. It has the benefit of HLSQ_VS_CNTL.CONSTLEN matching for VS and BS. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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958f6ffb60
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@ -871,6 +871,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
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}
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if (dirty & FD_DIRTY_PROG) {
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fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, 0x7);
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fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
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fd6_emit_add_group(emit, prog->binning_stateobj,
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FD6_GROUP_PROG_BINNING, 0x1);
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@ -1029,6 +1030,9 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
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OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
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OUT_RB(obj, state);
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/* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
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* de-duplicate this from program->config_stateobj
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*/
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OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
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OUT_RING(obj, mapping->num_ibo);
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@ -43,6 +43,7 @@ struct fd_ringbuffer;
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* need to be emit'd.
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*/
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enum fd6_state_id {
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FD6_GROUP_PROG_CONFIG,
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FD6_GROUP_PROG,
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FD6_GROUP_PROG_BINNING,
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FD6_GROUP_LRZ,
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@ -194,6 +194,50 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian
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COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
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}
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static void
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setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
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{
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OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
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OUT_RING(ring, 0xff); /* XXX */
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debug_assert(state->vs->constlen >= state->bs->constlen);
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OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
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OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
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A6XX_HLSQ_VS_CNTL_ENABLED);
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OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(0));
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OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(0));
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OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(0));
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OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
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OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
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A6XX_HLSQ_FS_CNTL_ENABLED);
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OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
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OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
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A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
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A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
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A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
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OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
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OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
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A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
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A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
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A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
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OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
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OUT_RING(ring, COND(false, A6XX_SP_HS_CONFIG_ENABLED));
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OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
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OUT_RING(ring, COND(false, A6XX_SP_DS_CONFIG_ENABLED));
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OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
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OUT_RING(ring, COND(false, A6XX_SP_GS_CONFIG_ENABLED));
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OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
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OUT_RING(ring, state->fs->image_mapping.num_ibo);
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}
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#define VALIDREG(r) ((r) != regid(63,0))
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#define CONDREG(r, val) COND(VALIDREG(r), (val))
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@ -271,29 +315,22 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
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* emitted if frag-prog is dirty vs if vert-prog is dirty..
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*/
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OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
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OUT_RING(ring, COND(vs, A6XX_SP_VS_CONFIG_ENABLED) |
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A6XX_SP_VS_CONFIG_NIBO(vs->image_mapping.num_ibo) |
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A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
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A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp)); /* SP_VS_CONFIG */
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OUT_PKT4(ring, REG_A6XX_SP_VS_INSTRLEN, 1);
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OUT_RING(ring, vs->instrlen); /* SP_VS_INSTRLEN */
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OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
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OUT_RING(ring, 0);
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OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
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OUT_RING(ring, 0); /* SP_HS_CONFIG */
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OUT_PKT4(ring, REG_A6XX_SP_HS_INSTRLEN, 1);
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OUT_RING(ring, 0); /* SP_HS_INSTRLEN */
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OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
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OUT_RING(ring, 0); /* SP_DS_CONFIG */
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OUT_PKT4(ring, REG_A6XX_SP_DS_INSTRLEN, 1);
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OUT_RING(ring, 0); /* SP_DS_INSTRLEN */
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OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
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OUT_RING(ring, 0);
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OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
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OUT_RING(ring, 0); /* SP_GS_CONFIG */
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OUT_PKT4(ring, REG_A6XX_SP_GS_INSTRLEN, 1);
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OUT_RING(ring, 0); /* SP_GS_INSTRLEN */
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/* I believe this is related to pre-dispatch texture fetch.. we probably
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@ -308,11 +345,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
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OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
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OUT_RING(ring, 0x5);
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OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
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OUT_RING(ring, COND(fs, A6XX_SP_FS_CONFIG_ENABLED) |
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A6XX_SP_FS_CONFIG_NIBO(fs->image_mapping.num_ibo) |
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A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
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A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp)); /* SP_FS_CONFIG */
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OUT_PKT4(ring, REG_A6XX_SP_FS_INSTRLEN, 1);
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OUT_RING(ring, fs->instrlen); /* SP_FS_INSTRLEN */
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OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
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@ -320,17 +353,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
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A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
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0xfc000000);
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OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
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OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
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A6XX_HLSQ_VS_CNTL_ENABLED);
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OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(0)); /* HLSQ_HS_CONSTLEN */
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OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(0)); /* HLSQ_DS_CONSTLEN */
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OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(0)); /* HLSQ_GS_CONSTLEN */
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OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
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OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
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A6XX_HLSQ_FS_CNTL_ENABLED);
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OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
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OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
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A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
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@ -460,9 +482,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
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OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
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OUT_RING(ring, 0); /* XXX */
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OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
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OUT_RING(ring, 0xff); /* XXX */
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OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
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OUT_RING(ring, 0x0000ffff); /* XXX */
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@ -677,9 +696,11 @@ fd6_program_create(void *data, struct ir3_shader_variant *bs,
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state->bs = bs;
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state->vs = vs;
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state->fs = fs;
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state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
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state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
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state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
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setup_config_stateobj(state->config_stateobj, state);
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setup_stateobj(state->binning_stateobj, state, key, true);
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setup_stateobj(state->stateobj, state, key, false);
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@ -692,6 +713,7 @@ fd6_program_destroy(void *data, struct ir3_program_state *state)
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struct fd6_program_state *so = fd6_program_state(state);
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fd_ringbuffer_del(so->stateobj);
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fd_ringbuffer_del(so->binning_stateobj);
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fd_ringbuffer_del(so->config_stateobj);
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free(so);
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}
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@ -48,6 +48,7 @@ struct fd6_program_state {
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struct ir3_shader_variant *bs; /* binning pass vs */
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struct ir3_shader_variant *vs;
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struct ir3_shader_variant *fs;
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struct fd_ringbuffer *config_stateobj;
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struct fd_ringbuffer *binning_stateobj;
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struct fd_ringbuffer *stateobj;
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