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radv: fix initializing the DS clear metadata value for separate aspects 

We shouldn't overwrite the clear value of the other aspect (in case
separate depth/stencil layouts are used).

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12222>
This commit is contained in:
Samuel Pitoiset 2021-08-05 17:47:02 +02:00 committed by Marge Bot
parent 9fe8ae3fcd
commit 1db36422b9
1 changed files with 1 additions and 5 deletions
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6
src/amd/vulkan/radv_cmd_buffer.c
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@ -6609,7 +6609,6 @@ static void
radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *range)
{
VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
struct radv_cmd_state *state = &cmd_buffer->state;
uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
VkClearDepthStencilValue value = {0};
@ -6625,10 +6624,7 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
if (vk_format_has_stencil(image->vk_format))
aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);
if (radv_image_is_tc_compat_htile(image) && (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)) {
/* Initialize the TC-compat metada value to 0 because by