intel/vec4: Remove everything related to VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
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@ -580,7 +580,6 @@ enum opcode {
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VS_OPCODE_URB_WRITE,
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VS_OPCODE_PULL_CONSTANT_LOAD,
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VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
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VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
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@ -824,15 +824,6 @@ namespace {
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0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
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0, 0);
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case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
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if (devinfo->gen >= 8)
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return calculate_desc(info, unit_fpu, 12 /* XXX */, 0, 0,
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4 /* XXX */, 0,
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0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
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0, 0);
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else
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abort();
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case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
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case TCS_OPCODE_GET_INSTANCE_ID:
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case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
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@ -456,9 +456,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
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case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
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return "pull_constant_load_gen7";
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case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
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return "set_simd4x2_header_gen9";
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case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
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return "unpack_flags_simd4x2";
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@ -285,7 +285,6 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
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case VEC4_OPCODE_SET_HIGH_32BIT:
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case VS_OPCODE_PULL_CONSTANT_LOAD:
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case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
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case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
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case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
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case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
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case TES_OPCODE_CREATE_INPUT_READ_HEADER:
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@ -1402,24 +1402,6 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
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}
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}
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static void
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generate_set_simd4x2_header_gen9(struct brw_codegen *p,
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vec4_instruction *,
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struct brw_reg dst)
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{
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brw_push_insn_state(p);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_set_default_exec_size(p, BRW_EXECUTE_8);
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brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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brw_MOV(p, get_element_ud(dst, 2),
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brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
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brw_pop_insn_state(p);
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}
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static void
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generate_mov_indirect(struct brw_codegen *p,
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vec4_instruction *,
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@ -1810,10 +1792,6 @@ generate_code(struct brw_codegen *p,
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send_count++;
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break;
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case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
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generate_set_simd4x2_header_gen9(p, inst, dst);
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break;
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case GS_OPCODE_URB_WRITE:
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generate_gs_urb_write(p, inst);
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send_count++;
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@ -873,7 +873,6 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
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/* The message header is necessary for:
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* - Gen4 (always)
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* - Gen9+ for selecting SIMD4x2
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* - Texel offsets
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* - Gather channel selection
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* - Sampler indices too large to fit in a 4-bit value.
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