From 1d71b1a311239ecbc2dbdd241abcf64a7345dc41 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 22 Sep 2020 13:21:17 -0700 Subject: [PATCH] intel/vec4: Remove everything related to VS_OPCODE_SET_SIMD4X2_HEADER_GEN9 Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_eu_defines.h | 1 - src/intel/compiler/brw_ir_performance.cpp | 9 --------- src/intel/compiler/brw_shader.cpp | 3 --- src/intel/compiler/brw_vec4.cpp | 1 - src/intel/compiler/brw_vec4_generator.cpp | 22 ---------------------- src/intel/compiler/brw_vec4_visitor.cpp | 1 - 6 files changed, 37 deletions(-) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 29ae95b8a38..870035d1a0b 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -580,7 +580,6 @@ enum opcode { VS_OPCODE_URB_WRITE, VS_OPCODE_PULL_CONSTANT_LOAD, VS_OPCODE_PULL_CONSTANT_LOAD_GEN7, - VS_OPCODE_SET_SIMD4X2_HEADER_GEN9, VS_OPCODE_UNPACK_FLAGS_SIMD4X2, diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index e95b847bd7f..eb36ae1eb9e 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -824,15 +824,6 @@ namespace { 0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */, 0, 0); - case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9: - if (devinfo->gen >= 8) - return calculate_desc(info, unit_fpu, 12 /* XXX */, 0, 0, - 4 /* XXX */, 0, - 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, - 0, 0); - else - abort(); - case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: case TCS_OPCODE_GET_INSTANCE_ID: case TCS_OPCODE_SET_INPUT_URB_OFFSETS: diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 2650e89040c..82f5506116c 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -456,9 +456,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: return "pull_constant_load_gen7"; - case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9: - return "set_simd4x2_header_gen9"; - case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: return "unpack_flags_simd4x2"; diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 878ee4e96e1..ef7b90bfbb2 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -285,7 +285,6 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo) case VEC4_OPCODE_SET_HIGH_32BIT: case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: - case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9: case TCS_OPCODE_SET_INPUT_URB_OFFSETS: case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: case TES_OPCODE_CREATE_INPUT_READ_HEADER: diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 3afaaedc70c..38c841fbaf2 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1402,24 +1402,6 @@ generate_pull_constant_load_gen7(struct brw_codegen *p, } } -static void -generate_set_simd4x2_header_gen9(struct brw_codegen *p, - vec4_instruction *, - struct brw_reg dst) -{ - brw_push_insn_state(p); - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - - brw_set_default_exec_size(p, BRW_EXECUTE_8); - brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); - - brw_set_default_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, get_element_ud(dst, 2), - brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2)); - - brw_pop_insn_state(p); -} - static void generate_mov_indirect(struct brw_codegen *p, vec4_instruction *, @@ -1810,10 +1792,6 @@ generate_code(struct brw_codegen *p, send_count++; break; - case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9: - generate_set_simd4x2_header_gen9(p, inst, dst); - break; - case GS_OPCODE_URB_WRITE: generate_gs_urb_write(p, inst); send_count++; diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp index 094ec54b298..e91f91f4adb 100644 --- a/src/intel/compiler/brw_vec4_visitor.cpp +++ b/src/intel/compiler/brw_vec4_visitor.cpp @@ -873,7 +873,6 @@ vec4_visitor::emit_texture(ir_texture_opcode op, /* The message header is necessary for: * - Gen4 (always) - * - Gen9+ for selecting SIMD4x2 * - Texel offsets * - Gather channel selection * - Sampler indices too large to fit in a 4-bit value.