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intel/vec4: Remove everything related to VS_OPCODE_SET_SIMD4X2_HEADER_GEN9 

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
This commit is contained in:
Ian Romanick 2020-09-22 13:21:17 -07:00
parent 2a49007411
commit 1d71b1a311
6 changed files with 0 additions and 37 deletions
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1
src/intel/compiler/brw_eu_defines.h
View File

@ -580,7 +580,6 @@ enum opcode {
VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

9
src/intel/compiler/brw_ir_performance.cpp
View File

@ -824,15 +824,6 @@ namespace {
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
0, 0);
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
if (devinfo->gen >= 8)
return calculate_desc(info, unit_fpu, 12 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
else
abort();
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
case TCS_OPCODE_GET_INSTANCE_ID:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:

3
src/intel/compiler/brw_shader.cpp
View File

@ -456,9 +456,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
return "pull_constant_load_gen7";
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
return "set_simd4x2_header_gen9";
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
return "unpack_flags_simd4x2";

1
src/intel/compiler/brw_vec4.cpp
View File

@ -285,7 +285,6 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
case VEC4_OPCODE_SET_HIGH_32BIT:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:

22
src/intel/compiler/brw_vec4_generator.cpp
View File

@ -1402,24 +1402,6 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
}
}
static void
generate_set_simd4x2_header_gen9(struct brw_codegen *p,
vec4_instruction *,
struct brw_reg dst)
{
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_element_ud(dst, 2),
brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
brw_pop_insn_state(p);
}
static void
generate_mov_indirect(struct brw_codegen *p,
vec4_instruction *,
@ -1810,10 +1792,6 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
generate_set_simd4x2_header_gen9(p, inst, dst);
break;
case GS_OPCODE_URB_WRITE:
generate_gs_urb_write(p, inst);
send_count++;

1
src/intel/compiler/brw_vec4_visitor.cpp
View File

@ -873,7 +873,6 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
/* The message header is necessary for:
* - Gen4 (always)
* - Gen9+ for selecting SIMD4x2
* - Texel offsets
* - Gather channel selection
* - Sampler indices too large to fit in a 4-bit value.