radv: port merge tess info from anv
anv merges the tess info correctly, but radv wasn't doing this.
This fixes hangs in
dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw
Fixes: 60fc0544e0
(radv/pipeline: handle tessellation shader compilation)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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d27aaae4d2
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@ -1769,6 +1769,45 @@ radv_fill_shader_keys(struct ac_shader_variant_key *keys,
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keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
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}
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static void
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merge_tess_info(struct shader_info *tes_info,
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const struct shader_info *tcs_info)
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{
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/* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
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*
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* "PointMode. Controls generation of points rather than triangles
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* or lines. This functionality defaults to disabled, and is
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* enabled if either shader stage includes the execution mode.
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*
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* and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
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* PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
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* and OutputVertices, it says:
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*
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* "One mode must be set in at least one of the tessellation
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* shader stages."
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*
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* So, the fields can be set in either the TCS or TES, but they must
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* agree if set in both. Our backend looks at TES, so bitwise-or in
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* the values from the TCS.
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*/
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assert(tcs_info->tess.tcs_vertices_out == 0 ||
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tes_info->tess.tcs_vertices_out == 0 ||
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tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
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tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
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assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
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tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
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tcs_info->tess.spacing == tes_info->tess.spacing);
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tes_info->tess.spacing |= tcs_info->tess.spacing;
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assert(tcs_info->tess.primitive_mode == 0 ||
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tes_info->tess.primitive_mode == 0 ||
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tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
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tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
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tes_info->tess.ccw |= tcs_info->tess.ccw;
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tes_info->tess.point_mode |= tcs_info->tess.point_mode;
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}
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static
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void radv_create_shaders(struct radv_pipeline *pipeline,
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struct radv_device *device,
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@ -1872,6 +1911,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
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if (nir[MESA_SHADER_TESS_CTRL]) {
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nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
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merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
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}
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radv_link_shaders(pipeline, nir);
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