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radv: Allow radv_fill_buffer to work with VAs only 

Makes the bo parameter optional which is useful
for the clears performed by acceleration structure
build commands.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16517>
This commit is contained in:
Konstantin Seurer 2022-05-15 12:43:35 +02:00 committed by Marge Bot
parent 61d5594064
commit 183c15dbb2
5 changed files with 26 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/amd/vulkan/radv_cmd_buffer.c
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@ -8231,7 +8231,8 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
/* Initialize the mipmap levels without DCC. */ /* Initialize the mipmap levels without DCC. */
if (size != image->planes[0].surface.meta_size) { if (size != image->planes[0].surface.meta_size) {
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo,
image->offset + image->planes[0].surface.meta_offset + size, radv_buffer_get_va(image->bo) + image->offset +
image->planes[0].surface.meta_offset + size,
image->planes[0].surface.meta_size - size, 0xffffffff); image->planes[0].surface.meta_size - size, 0xffffffff);
} }
} }

12
src/amd/vulkan/radv_meta_buffer.c
View File

@ -238,7 +238,7 @@ radv_prefer_compute_dma(const struct radv_device *device, uint64_t size,
if (device->physical_device->rad_info.gfx_level >= GFX10 && if (device->physical_device->rad_info.gfx_level >= GFX10 &&
device->physical_device->rad_info.has_dedicated_vram) { device->physical_device->rad_info.has_dedicated_vram) {
if ((src_bo && !(src_bo->initial_domain & RADEON_DOMAIN_VRAM)) || if ((src_bo && !(src_bo->initial_domain & RADEON_DOMAIN_VRAM)) ||
!(dst_bo->initial_domain & RADEON_DOMAIN_VRAM)) { (dst_bo && !(dst_bo->initial_domain & RADEON_DOMAIN_VRAM))) {
/* Prefer CP DMA for GTT on dGPUS due to slow PCIe. */ /* Prefer CP DMA for GTT on dGPUS due to slow PCIe. */
use_compute = false; use_compute = false;
} }
@ -249,16 +249,15 @@ radv_prefer_compute_dma(const struct radv_device *device, uint64_t size,
uint32_t uint32_t
radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, uint32_t value) struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value)
{ {
bool use_compute = radv_prefer_compute_dma(cmd_buffer->device, size, NULL, bo); bool use_compute = radv_prefer_compute_dma(cmd_buffer->device, size, NULL, bo);
uint32_t flush_bits = 0; uint32_t flush_bits = 0;
assert(!(offset & 3)); assert(!(va & 3));
assert(!(size & 3)); assert(!(size & 3));
uint64_t va = radv_buffer_get_va(bo) + offset; if (bo)
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo); radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo);
if (use_compute) { if (use_compute) {
@ -305,7 +304,8 @@ radv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSi
if (fillSize == VK_WHOLE_SIZE) if (fillSize == VK_WHOLE_SIZE)
fillSize = (dst_buffer->size - dstOffset) & ~3ull; fillSize = (dst_buffer->size - dstOffset) & ~3ull;
radv_fill_buffer(cmd_buffer, NULL, dst_buffer->bo, dst_buffer->offset + dstOffset, fillSize, radv_fill_buffer(cmd_buffer, NULL, dst_buffer->bo,
radv_buffer_get_va(dst_buffer->bo) + dst_buffer->offset + dstOffset, fillSize,
data); data);
} }

15
src/amd/vulkan/radv_meta_clear.c
View File

@ -1278,7 +1278,8 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
size = slice_size * radv_get_layerCount(image, range); size = slice_size * radv_get_layerCount(image, range);
} }
return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset,
size, value);
} }
uint32_t uint32_t
@ -1295,7 +1296,8 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
offset += slice_size * range->baseArrayLayer; offset += slice_size * range->baseArrayLayer;
size = slice_size * radv_get_layerCount(image, range); size = slice_size * radv_get_layerCount(image, range);
return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset,
size, value);
} }
uint32_t uint32_t
@ -1342,7 +1344,8 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
if (!size) if (!size)
continue; continue;
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo,
radv_buffer_get_va(image->bo) + offset, size, value);
} }
return flush_bits; return flush_bits;
@ -1487,7 +1490,8 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (htile_mask == UINT_MAX) { if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */ /* Clear the whole HTILE buffer. */
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo,
radv_buffer_get_va(image->bo) + offset, size, value);
} else { } else {
/* Only clear depth or stencil bytes in the HTILE buffer. */ /* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits |= flush_bits |=
@ -1502,7 +1506,8 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (htile_mask == UINT_MAX) { if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */ /* Clear the whole HTILE buffer. */
flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo,
radv_buffer_get_va(image->bo) + offset, size, value);
} else { } else {
/* Only clear depth or stencil bytes in the HTILE buffer. */ /* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits = flush_bits =

3
src/amd/vulkan/radv_private.h
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@ -1675,8 +1675,7 @@ enum radv_cmd_flush_bits radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffe
VkAccessFlags2 dst_flags, VkAccessFlags2 dst_flags,
const struct radv_image *image); const struct radv_image *image);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value);
uint32_t value);
void radv_fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, void radv_fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size,
uint32_t data); uint32_t data);
void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo,

9
src/amd/vulkan/radv_query.c
View File

@ -1364,12 +1364,15 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin
*/ */
cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, firstQuery * pool->stride, flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,
radv_buffer_get_va(pool->bo) + firstQuery * pool->stride,
queryCount * pool->stride, value); queryCount * pool->stride, value);
if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) { if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, flush_bits |=
pool->availability_offset + firstQuery * 4, queryCount * 4, 0); radv_fill_buffer(cmd_buffer, NULL, pool->bo,
radv_buffer_get_va(pool->bo) + pool->availability_offset + firstQuery * 4,
queryCount * 4, 0);
} }
if (flush_bits) { if (flush_bits) {