From 183c15dbb2f9dfec48f5ce7486551e223ca89401 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Sun, 15 May 2022 12:43:35 +0200 Subject: [PATCH] radv: Allow radv_fill_buffer to work with VAs only Makes the bo parameter optional which is useful for the clears performed by acceleration structure build commands. Signed-off-by: Konstantin Seurer Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 3 ++- src/amd/vulkan/radv_meta_buffer.c | 14 +++++++------- src/amd/vulkan/radv_meta_clear.c | 15 ++++++++++----- src/amd/vulkan/radv_private.h | 3 +-- src/amd/vulkan/radv_query.c | 9 ++++++--- 5 files changed, 26 insertions(+), 18 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index fbe7f9fd6a8..84e9adb11ec 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8231,7 +8231,8 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, /* Initialize the mipmap levels without DCC. */ if (size != image->planes[0].surface.meta_size) { flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, - image->offset + image->planes[0].surface.meta_offset + size, + radv_buffer_get_va(image->bo) + image->offset + + image->planes[0].surface.meta_offset + size, image->planes[0].surface.meta_size - size, 0xffffffff); } } diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index 306cb6c249a..11396ae638a 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -238,7 +238,7 @@ radv_prefer_compute_dma(const struct radv_device *device, uint64_t size, if (device->physical_device->rad_info.gfx_level >= GFX10 && device->physical_device->rad_info.has_dedicated_vram) { if ((src_bo && !(src_bo->initial_domain & RADEON_DOMAIN_VRAM)) || - !(dst_bo->initial_domain & RADEON_DOMAIN_VRAM)) { + (dst_bo && !(dst_bo->initial_domain & RADEON_DOMAIN_VRAM))) { /* Prefer CP DMA for GTT on dGPUS due to slow PCIe. */ use_compute = false; } @@ -249,17 +249,16 @@ radv_prefer_compute_dma(const struct radv_device *device, uint64_t size, uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, - struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, uint32_t value) + struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value) { bool use_compute = radv_prefer_compute_dma(cmd_buffer->device, size, NULL, bo); uint32_t flush_bits = 0; - assert(!(offset & 3)); + assert(!(va & 3)); assert(!(size & 3)); - uint64_t va = radv_buffer_get_va(bo) + offset; - - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo); + if (bo) + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo); if (use_compute) { cmd_buffer->state.flush_bits |= @@ -305,7 +304,8 @@ radv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSi if (fillSize == VK_WHOLE_SIZE) fillSize = (dst_buffer->size - dstOffset) & ~3ull; - radv_fill_buffer(cmd_buffer, NULL, dst_buffer->bo, dst_buffer->offset + dstOffset, fillSize, + radv_fill_buffer(cmd_buffer, NULL, dst_buffer->bo, + radv_buffer_get_va(dst_buffer->bo) + dst_buffer->offset + dstOffset, fillSize, data); } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 2b0e97b29d3..5c441d50411 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1278,7 +1278,8 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, size = slice_size * radv_get_layerCount(image, range); } - return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset, + size, value); } uint32_t @@ -1295,7 +1296,8 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, offset += slice_size * range->baseArrayLayer; size = slice_size * radv_get_layerCount(image, range); - return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + return radv_fill_buffer(cmd_buffer, image, image->bo, radv_buffer_get_va(image->bo) + offset, + size, value); } uint32_t @@ -1342,7 +1344,8 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, if (!size) continue; - flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, + radv_buffer_get_va(image->bo) + offset, size, value); } return flush_bits; @@ -1487,7 +1490,8 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im if (htile_mask == UINT_MAX) { /* Clear the whole HTILE buffer. */ - flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, + radv_buffer_get_va(image->bo) + offset, size, value); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ flush_bits |= @@ -1502,7 +1506,8 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im if (htile_mask == UINT_MAX) { /* Clear the whole HTILE buffer. */ - flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, + radv_buffer_get_va(image->bo) + offset, size, value); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ flush_bits = diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index fed95ce1594..f80095e1949 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1675,8 +1675,7 @@ enum radv_cmd_flush_bits radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffe VkAccessFlags2 dst_flags, const struct radv_image *image); uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, - struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, - uint32_t value); + struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value); void radv_fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, uint32_t data); void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index a56961a264f..074ab33be5b 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1364,12 +1364,15 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin */ cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; - flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, firstQuery * pool->stride, + flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, + radv_buffer_get_va(pool->bo) + firstQuery * pool->stride, queryCount * pool->stride, value); if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) { - flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo, - pool->availability_offset + firstQuery * 4, queryCount * 4, 0); + flush_bits |= + radv_fill_buffer(cmd_buffer, NULL, pool->bo, + radv_buffer_get_va(pool->bo) + pool->availability_offset + firstQuery * 4, + queryCount * 4, 0); } if (flush_bits) {