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radeon/uvd: fall back to shader based decoding for MPEG2 on UVD 2.x v2 

UVD 2.x doesn't support hardware decoding of MPEG2, just use shader
based decoding for those chipsets.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66450

v2: fix interlacing as well

Signed-off-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Christian König 2013-07-10 15:43:16 +02:00
parent 649ef4da30
commit 1681bd7f2b
2 changed files with 19 additions and 5 deletions
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19
src/gallium/drivers/r600/r600_uvd.c
View File

@ -184,10 +184,21 @@ int r600_uvd_get_video_param(struct pipe_screen *screen,
{
struct r600_screen *rscreen = (struct r600_screen *)screen;
/* No support for MPEG4 on UVD 2.x */
if (param == PIPE_VIDEO_CAP_SUPPORTED && rscreen->family < CHIP_PALM &&
u_reduce_video_profile(profile) == PIPE_VIDEO_CODEC_MPEG4)
return false;
/* UVD 2.x limits */
if (rscreen->family < CHIP_PALM) {
enum pipe_video_codec codec = u_reduce_video_profile(profile);
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
/* no support for MPEG4 */
return codec != PIPE_VIDEO_CODEC_MPEG4;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
/* and MPEG2 only with shaders */
return codec != PIPE_VIDEO_CODEC_MPEG12;
default:
break;
}
}
return ruvd_get_video_param(screen, profile, param);
}

5
src/gallium/drivers/radeon/radeon_uvd.c
View File

@ -828,13 +828,16 @@ struct pipe_video_decoder *ruvd_create_decoder(struct pipe_context *context,
ruvd_set_dtb set_dtb)
{
unsigned dpb_size = calc_dpb_size(profile, width, height, max_references);
struct radeon_info info;
struct ruvd_decoder *dec;
struct ruvd_msg msg;
int i;
ws->query_info(ws, &info);
switch(u_reduce_video_profile(profile)) {
case PIPE_VIDEO_CODEC_MPEG12:
if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
return vl_create_mpeg12_decoder(context, profile, entrypoint,
chroma_format, width,
height, max_references, expect_chunked_decode);