vc4: Track clears veresus uncleared draws, and the clear color.
This is a step toward queueing more than one draw per frame. Fixes piglit attribute0 test, since we get a working clear color now.
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9c631f30c9
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165ca6b5ad
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@ -89,14 +89,22 @@ vc4_setup_rcl(struct vc4_context *vc4)
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{
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struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
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struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
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uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared;
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uint32_t width = vc4->framebuffer.width;
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uint32_t height = vc4->framebuffer.height;
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uint32_t xtiles = align(width, 64) / 64;
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uint32_t ytiles = align(height, 64) / 64;
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#if 0
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fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n",
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vc4->resolve,
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vc4->cleared,
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resolve_uncleared);
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#endif
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cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
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cl_u32(&vc4->rcl, 0xff000000); // Opaque Black
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cl_u32(&vc4->rcl, 0xff000000); // 32 bit clear colours need to be repeated twice
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cl_u32(&vc4->rcl, vc4->clear_color[0]);
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cl_u32(&vc4->rcl, vc4->clear_color[1]);
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cl_u32(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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@ -109,24 +117,30 @@ vc4_setup_rcl(struct vc4_context *vc4)
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VC4_RENDER_CONFIG_FORMAT_RGBA8888));
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cl_u8(&vc4->rcl, 0);
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// Do a store of the first tile to force the tile buffer to be cleared
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/* XXX: I think these two packets may be unnecessary. */
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if (0) {
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/* The tile buffer normally gets cleared when the previous tile is
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* stored. If the clear values changed between frames, then the tile
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* buffer has stale clear values in it, so we have to do a store in
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* None mode (no writes) so that we trigger the tile buffer clear.
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*/
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if (vc4->cleared & PIPE_CLEAR_COLOR0) {
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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cl_u16(&vc4->rcl, 0); // Store nothing (just clear)
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cl_u32(&vc4->rcl, 0); // no address is needed
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cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
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cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
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}
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for (int x = 0; x < xtiles; x++) {
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for (int y = 0; y < ytiles; y++) {
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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cl_u8(&vc4->rcl, x);
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cl_u8(&vc4->rcl, y);
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bool end_of_frame = (x == xtiles - 1 &&
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y == ytiles - 1);
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/* Note that the load doesn't actually occur until the
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* tile coords packet is processed.
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*/
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if (resolve_uncleared & PIPE_CLEAR_COLOR) {
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cl_start_reloc(&vc4->rcl, 1);
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cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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cl_u8(&vc4->rcl,
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@ -134,20 +148,30 @@ vc4_setup_rcl(struct vc4_context *vc4)
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VC4_LOADSTORE_TILE_BUFFER_FORMAT_RASTER);
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cl_u8(&vc4->rcl,
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VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
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cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset);
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cl_reloc(vc4, &vc4->rcl, ctex->bo,
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csurf->offset);
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}
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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cl_u8(&vc4->rcl, x);
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cl_u8(&vc4->rcl, y);
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cl_start_reloc(&vc4->rcl, 1);
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cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST);
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cl_reloc(vc4, &vc4->rcl, vc4->tile_alloc,
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(y * xtiles + x) * 32);
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if (x == xtiles - 1 && y == ytiles - 1) {
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if (vc4->resolve & PIPE_CLEAR_COLOR0) {
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if (end_of_frame) {
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cl_u8(&vc4->rcl,
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VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
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} else {
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cl_u8(&vc4->rcl,
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VC4_PACKET_STORE_MS_TILE_BUFFER);
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}
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} else {
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assert(!"unfinished: Need to end the frame\n");
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}
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}
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}
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}
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@ -168,6 +192,7 @@ vc4_flush(struct pipe_context *pctx)
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struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
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struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
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struct drm_vc4_submit_cl submit;
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memset(&submit, 0, sizeof(submit));
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@ -207,7 +232,10 @@ vc4_flush(struct pipe_context *pctx)
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vc4->shader_rec_count = 0;
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vc4->needs_flush = false;
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vc4->draw_call_queued = false;
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vc4->dirty = ~0;
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vc4->resolve = 0;
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vc4->cleared = 0;
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dump_fbo(vc4, ctex->bo);
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}
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@ -136,6 +136,15 @@ struct vc4_context {
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/** bitfield of VC4_DIRTY_* */
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uint32_t dirty;
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/* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
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* first rendering.
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*/
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uint32_t cleared;
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/* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
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* (either clears or draws).
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*/
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uint32_t resolve;
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uint32_t clear_color[2];
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/**
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* Set if some drawing (triangles, blits, or just a glClear()) has
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@ -144,6 +153,12 @@ struct vc4_context {
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*/
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bool needs_flush;
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/**
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* Set when needs_flush, and the queued rendering is not just composed
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* of full-buffer clears.
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*/
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bool draw_call_queued;
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struct primconvert_context *primconvert;
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struct util_hash_table *fs_cache, *vs_cache;
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@ -25,22 +25,20 @@
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#include <stdio.h>
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#include "util/u_format.h"
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#include "util/u_pack_color.h"
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#include "indices/u_primconvert.h"
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#include "vc4_context.h"
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#include "vc4_resource.h"
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/**
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* Does the initial bining command list setup for drawing to a given FBO.
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*/
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static void
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vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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vc4_start_draw(struct vc4_context *vc4)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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if (info->mode >= PIPE_PRIM_QUADS) {
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util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
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util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
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util_primconvert_draw_vbo(vc4->primconvert, info);
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if (vc4->needs_flush)
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return;
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}
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uint32_t width = vc4->framebuffer.width;
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uint32_t height = vc4->framebuffer.height;
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@ -60,10 +58,6 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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"tile_state");
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}
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vc4_update_compiled_shaders(vc4);
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vc4->needs_flush = true;
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// Tile state data is 48 bytes per tile, I think it can be thrown away
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// as soon as binning is finished.
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cl_start_reloc(&vc4->bcl, 2);
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@ -80,6 +74,25 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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cl_u8(&vc4->bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
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cl_u8(&vc4->bcl, 0x12); // 16 bit triangle
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vc4->needs_flush = true;
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vc4->draw_call_queued = true;
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}
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static void
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vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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if (info->mode >= PIPE_PRIM_QUADS) {
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util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
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util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
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util_primconvert_draw_vbo(vc4->primconvert, info);
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return;
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}
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vc4_start_draw(vc4);
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vc4_update_compiled_shaders(vc4);
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vc4_emit_state(pctx);
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/* the actual draw call. */
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@ -168,19 +181,46 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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cl_u8(&vc4->shader_rec, i * 16); /* CS VPM offset */
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}
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if (vc4->zsa && vc4->zsa->depth.enabled) {
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vc4->resolve |= PIPE_CLEAR_DEPTH;
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}
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vc4->resolve |= PIPE_CLEAR_COLOR0;
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vc4->shader_rec_count++;
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vc4_flush(pctx);
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}
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static uint32_t
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pack_rgba(enum pipe_format format, const float *rgba)
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{
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union util_color uc;
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util_pack_color(rgba, format, &uc);
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return uc.ui[0];
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}
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static void
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vc4_clear(struct pipe_context *pctx, unsigned buffers,
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const union pipe_color_union *color, double depth, unsigned stencil)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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vc4->needs_flush = true;
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/* We can't flag new buffers for clearing once we've queued draws. We
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* could avoid this by using the 3d engine to clear.
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*/
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if (vc4->draw_call_queued)
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vc4_flush(pctx);
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if (buffers & PIPE_CLEAR_COLOR0) {
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vc4->clear_color[0] = vc4->clear_color[1] =
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pack_rgba(vc4->framebuffer.cbufs[0]->format,
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color->f);
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}
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vc4->cleared |= buffers;
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vc4->resolve |= buffers;
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vc4_start_draw(vc4);
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}
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static void
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