vc4: Move the rest of RCL setup to flush time.
We only want to set up render target config and clear colors once per frame.
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100e5679c7
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@ -85,7 +85,7 @@ dump_fbo(struct vc4_context *vc4, struct vc4_bo *fbo)
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}
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static void
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vc4_rcl_tile_calls(struct vc4_context *vc4)
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vc4_setup_rcl(struct vc4_context *vc4)
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{
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struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
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struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
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@ -94,6 +94,33 @@ vc4_rcl_tile_calls(struct vc4_context *vc4)
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uint32_t xtiles = align(width, 64) / 64;
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uint32_t ytiles = align(height, 64) / 64;
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cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
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cl_u32(&vc4->rcl, 0xff000000); // Opaque Black
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cl_u32(&vc4->rcl, 0xff000000); // 32 bit clear colours need to be repeated twice
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cl_u32(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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cl_start_reloc(&vc4->rcl, 1);
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset);
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cl_u16(&vc4->rcl, width);
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cl_u16(&vc4->rcl, height);
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cl_u8(&vc4->rcl, (VC4_RENDER_CONFIG_MEMORY_FORMAT_LINEAR |
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VC4_RENDER_CONFIG_FORMAT_RGBA8888));
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cl_u8(&vc4->rcl, 0);
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// Do a store of the first tile to force the tile buffer to be cleared
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/* XXX: I think these two packets may be unnecessary. */
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if (0) {
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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cl_u16(&vc4->rcl, 0); // Store nothing (just clear)
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cl_u32(&vc4->rcl, 0); // no address is needed
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}
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for (int x = 0; x < xtiles; x++) {
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for (int y = 0; y < ytiles; y++) {
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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@ -137,13 +164,13 @@ vc4_flush(struct pipe_context *pctx)
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cl_u8(&vc4->bcl, VC4_PACKET_NOP);
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cl_u8(&vc4->bcl, VC4_PACKET_HALT);
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vc4_setup_rcl(vc4);
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struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
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struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
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struct drm_vc4_submit_cl submit;
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memset(&submit, 0, sizeof(submit));
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vc4_rcl_tile_calls(vc4);
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submit.bo_handles = vc4->bo_handles.base;
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submit.bo_handle_count = (vc4->bo_handles.next -
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vc4->bo_handles.base) / 4;
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@ -171,36 +171,6 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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vc4->shader_rec_count++;
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cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
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cl_u32(&vc4->rcl, 0xff000000); // Opaque Black
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cl_u32(&vc4->rcl, 0xff000000); // 32 bit clear colours need to be repeated twice
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cl_u32(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
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struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
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cl_start_reloc(&vc4->rcl, 1);
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset);
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cl_u16(&vc4->rcl, width);
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cl_u16(&vc4->rcl, height);
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cl_u8(&vc4->rcl, (VC4_RENDER_CONFIG_MEMORY_FORMAT_LINEAR |
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VC4_RENDER_CONFIG_FORMAT_RGBA8888));
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cl_u8(&vc4->rcl, 0);
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// Do a store of the first tile to force the tile buffer to be cleared
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/* XXX: I think these two packets may be unnecessary. */
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if (0) {
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cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, 0);
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cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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cl_u16(&vc4->rcl, 0); // Store nothing (just clear)
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cl_u32(&vc4->rcl, 0); // no address is needed
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}
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vc4_flush(pctx);
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}
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