From 165b016bbeedd4e8d1517a5e95949871cc55a123 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 8 Apr 2022 11:45:11 +1000 Subject: [PATCH] radv: use flush vgt streamout like PAL does. This uses WRITE_DATA on the ME engine to reset the register, to match what PAL does on GFX9+. This fixes KHR-GL45.transform_feedback_overflow_query_ARB.multiple-streams-one-buffer-per-stream on zink/radv. Reviewed-by: Samuel Pitoiset Cc: mesa-stable Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 34d8a69aaec..bedc13ce164 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -8779,7 +8779,14 @@ radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer) unsigned reg_strmout_cntl; /* The register is at different places on different ASICs. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; + radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); + radeon_emit(cs, S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME)); + radeon_emit(cs, R_0300FC_CP_STRMOUT_CNTL >> 2); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL; radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); } else {