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i965: Get rid of backend_instruction::sampler 

The generators no longer use this.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Chris Forbes 2014-08-03 21:40:00 +12:00
parent 298da9fa2a
commit 0f4c5a70c6
7 changed files with 0 additions and 11 deletions
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1
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
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@ -83,7 +83,6 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
inst->base_mrf = base_mrf;
inst->mlen = msg_length;
inst->sampler = 0;
inst->header_present = false;
insts.push_tail(inst);

1
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -348,7 +348,6 @@ fs_inst::equals(fs_inst *inst) const
conditional_mod == inst->conditional_mod &&
mlen == inst->mlen &&
base_mrf == inst->base_mrf &&
sampler == inst->sampler &&
target == inst->target &&
eot == inst->eot &&
header_present == inst->header_present &&

1
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
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@ -157,7 +157,6 @@ instructions_match(fs_inst *a, fs_inst *b)
a->mlen == b->mlen &&
a->regs_written == b->regs_written &&
a->base_mrf == b->base_mrf &&
a->sampler == b->sampler &&
a->eot == b->eot &&
a->header_present == b->header_present &&
a->shadow_compare == b->shadow_compare)

1
src/mesa/drivers/dri/i965/brw_fs_fp.cpp
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@ -498,7 +498,6 @@ fs_visitor::emit_fragment_program_code()
inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy, fpi->TexSrcUnit);
}
inst->sampler = fpi->TexSrcUnit;
inst->shadow_compare = fpi->TexShadow;
/* Reuse the GLSL swizzle_result() handler. */

3
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
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@ -1745,7 +1745,6 @@ fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, uint32_t sampler)
inst->regs_written = 4; /* we only care about one reg of response,
* but the sampler always writes 4/8
*/
inst->sampler = sampler;
return dest;
}
@ -1867,8 +1866,6 @@ fs_visitor::visit(ir_texture *ir)
if (ir->op == ir_tg4)
inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
inst->sampler = sampler;
if (ir->shadow_comparitor)
inst->shadow_compare = true;

1
src/mesa/drivers/dri/i965/brw_shader.h
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@ -108,7 +108,6 @@ struct backend_instruction {
uint32_t texture_offset; /**< Texture offset bitfield */
uint32_t offset; /**< spill/unspill offset */
uint8_t sampler;
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
uint8_t target; /**< MRT target. */

3
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View File

@ -45,7 +45,6 @@ vec4_instruction::vec4_instruction(vec4_visitor *v,
this->no_dd_check = false;
this->writes_accumulator = false;
this->conditional_mod = BRW_CONDITIONAL_NONE;
this->sampler = 0;
this->texture_offset = 0;
this->target = 0;
this->shadow_compare = false;
@ -2282,7 +2281,6 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t sample
vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF_MCS);
inst->base_mrf = 2;
inst->mlen = 1;
inst->sampler = sampler;
inst->dst = dst_reg(this, glsl_type::uvec4_type);
inst->dst.writemask = WRITEMASK_XYZW;
@ -2434,7 +2432,6 @@ vec4_visitor::visit(ir_texture *ir)
sampler >= 16;
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->sampler = sampler;
inst->dst = dst_reg(this, ir->type);
inst->dst.writemask = WRITEMASK_XYZW;
inst->shadow_compare = ir->shadow_comparitor != NULL;