From 05eb9530ca4e06f124f79bd03cbd531eb2ce4b8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 26 May 2022 11:55:08 -0400 Subject: [PATCH] ac/gpu_info: always retile DCC on gfx10 and newer chips Unaligned DCC doesn't work there. Fixes: f8cf5ea982a - amd: add support for gfx1036 and gfx1037 chips Reviewed-by: Mihai Preda Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 3 ++- src/amd/common/ac_surface.c | 19 ------------------- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ffcdc4a4a37..e867228dec0 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1120,7 +1120,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR)) || info->gfx_level >= GFX10_3) { - if (info->max_render_backends == 1) + /* GFX10+ requires retiling in all cases. */ + if (info->max_render_backends == 1 && info->gfx_level == GFX9) info->use_display_dcc_unaligned = true; else info->use_display_dcc_with_retile_blit = true; diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b83fbdfdcbb..69c8f2d6dd9 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -358,12 +358,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) if (info->gfx_level >= GFX10_3) { - if (info->max_render_backends == 1) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) - } - ADD_MOD(AMD_FMT_MOD | common_dcc | AMD_FMT_MOD_SET(DCC_RETILE, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | @@ -373,13 +367,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->gfx_level >= GFX10_3) { bool independent_128b = info->gfx_level >= GFX10_3; - if (info->max_render_backends == 1) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)) - } - ADD_MOD(AMD_FMT_MOD | common_dcc | AMD_FMT_MOD_SET(DCC_RETILE, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | @@ -454,12 +441,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1)); /* Displayable modifiers are next. */ - /* These two will only be used by chips with 1 RB, and they are the best choice there. */ - if (info->max_render_backends == 1) { - ADD_MOD(modifier_dcc_best) - ADD_MOD(modifier_dcc_4k) - } - /* Add other displayable DCC settings. (DCC_RETILE implies displayable on all chips) */ ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)) ADD_MOD(modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1))