pan/bi: Update bi_count_write_registers for Valhall
We add some new instructions on Valhall with special register requirements (texturing, atomics). Handle these appropriately so we can do RA on Valhall. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
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@ -101,12 +101,32 @@ unsigned
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bi_count_write_registers(const bi_instr *ins, unsigned d)
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bi_count_write_registers(const bi_instr *ins, unsigned d)
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{
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{
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if (d == 0 && bi_opcode_props[ins->op].sr_write) {
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if (d == 0 && bi_opcode_props[ins->op].sr_write) {
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/* TODO: this special case is even more special, TEXC has a
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switch (ins->op) {
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* generic write mask stuffed in the desc... */
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case BI_OPCODE_TEXC:
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if (ins->op == BI_OPCODE_TEXC)
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if (ins->sr_count_2)
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return 4;
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return ins->sr_count;
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else
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else
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return bi_is_regfmt_16(ins->register_format) ? 2 : 4;
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case BI_OPCODE_TEX_SINGLE:
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case BI_OPCODE_TEX_FETCH:
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case BI_OPCODE_TEX_GATHER: {
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unsigned chans = util_bitcount(ins->write_mask);
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return bi_is_regfmt_16(ins->register_format) ?
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DIV_ROUND_UP(chans, 2) : chans;
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}
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case BI_OPCODE_ACMPXCHG_I32:
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/* Reads 2 but writes 1 */
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return 1;
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case BI_OPCODE_ATOM1_RETURN_I32:
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/* Allow omitting the destination for plain ATOM1 */
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return bi_is_null(ins->dest[0]) ? 0 : ins->sr_count;
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default:
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return bi_count_staging_registers(ins);
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return bi_count_staging_registers(ins);
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}
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} else if (ins->op == BI_OPCODE_SEG_ADD_I64) {
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} else if (ins->op == BI_OPCODE_SEG_ADD_I64) {
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return 2;
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return 2;
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} else if (ins->op == BI_OPCODE_TEXC && d == 1) {
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} else if (ins->op == BI_OPCODE_TEXC && d == 1) {
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