From 04a1df8c65de410ea3dd0283f3d8e045fb706d92 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 23 Mar 2022 12:05:10 -0400 Subject: [PATCH] pan/bi: Update bi_count_write_registers for Valhall We add some new instructions on Valhall with special register requirements (texturing, atomics). Handle these appropriately so we can do RA on Valhall. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/bifrost/bir.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/src/panfrost/bifrost/bir.c b/src/panfrost/bifrost/bir.c index d7106a23aae..cf568693251 100644 --- a/src/panfrost/bifrost/bir.c +++ b/src/panfrost/bifrost/bir.c @@ -101,12 +101,32 @@ unsigned bi_count_write_registers(const bi_instr *ins, unsigned d) { if (d == 0 && bi_opcode_props[ins->op].sr_write) { - /* TODO: this special case is even more special, TEXC has a - * generic write mask stuffed in the desc... */ - if (ins->op == BI_OPCODE_TEXC) - return 4; - else + switch (ins->op) { + case BI_OPCODE_TEXC: + if (ins->sr_count_2) + return ins->sr_count; + else + return bi_is_regfmt_16(ins->register_format) ? 2 : 4; + + case BI_OPCODE_TEX_SINGLE: + case BI_OPCODE_TEX_FETCH: + case BI_OPCODE_TEX_GATHER: { + unsigned chans = util_bitcount(ins->write_mask); + + return bi_is_regfmt_16(ins->register_format) ? + DIV_ROUND_UP(chans, 2) : chans; + } + + case BI_OPCODE_ACMPXCHG_I32: + /* Reads 2 but writes 1 */ + return 1; + + case BI_OPCODE_ATOM1_RETURN_I32: + /* Allow omitting the destination for plain ATOM1 */ + return bi_is_null(ins->dest[0]) ? 0 : ins->sr_count; + default: return bi_count_staging_registers(ins); + } } else if (ins->op == BI_OPCODE_SEG_ADD_I64) { return 2; } else if (ins->op == BI_OPCODE_TEXC && d == 1) {