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pan/bi: Update bi_count_write_registers for Valhall 

We add some new instructions on Valhall with special register requirements
(texturing, atomics). Handle these appropriately so we can do RA on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
This commit is contained in:
Alyssa Rosenzweig 2022-03-23 12:05:10 -04:00 committed by Marge Bot
parent 8b13ee75ba
commit 04a1df8c65
1 changed files with 25 additions and 5 deletions
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30
src/panfrost/bifrost/bir.c
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@ -101,12 +101,32 @@ unsigned
bi_count_write_registers(const bi_instr *ins, unsigned d)
{
if (d == 0 && bi_opcode_props[ins->op].sr_write) {
/* TODO: this special case is even more special, TEXC has a
* generic write mask stuffed in the desc... */
if (ins->op == BI_OPCODE_TEXC)
return 4;
else
switch (ins->op) {
case BI_OPCODE_TEXC:
if (ins->sr_count_2)
return ins->sr_count;
else
return bi_is_regfmt_16(ins->register_format) ? 2 : 4;
case BI_OPCODE_TEX_SINGLE:
case BI_OPCODE_TEX_FETCH:
case BI_OPCODE_TEX_GATHER: {
unsigned chans = util_bitcount(ins->write_mask);
return bi_is_regfmt_16(ins->register_format) ?
DIV_ROUND_UP(chans, 2) : chans;
}
case BI_OPCODE_ACMPXCHG_I32:
/* Reads 2 but writes 1 */
return 1;
case BI_OPCODE_ATOM1_RETURN_I32:
/* Allow omitting the destination for plain ATOM1 */
return bi_is_null(ins->dest[0]) ? 0 : ins->sr_count;
default:
return bi_count_staging_registers(ins);
}
} else if (ins->op == BI_OPCODE_SEG_ADD_I64) {
return 2;
} else if (ins->op == BI_OPCODE_TEXC && d == 1) {