freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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/*
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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "util/u_math.h"
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#include "ir3.h"
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/*
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* Instruction Scheduling:
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*
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2015-11-30 20:52:26 +00:00
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* A recursive depth based scheduling algo. Recursively find an eligible
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* instruction to schedule from the deepest instruction (recursing through
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* it's unscheduled src instructions). Normally this would result in a
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* lot of re-traversal of the same instructions, so we cache results in
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* instr->data (and clear cached results that would be no longer valid
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* after scheduling an instruction).
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2014-07-25 14:50:34 +01:00
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*
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* There are a few special cases that need to be handled, since sched
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* is currently independent of register allocation. Usages of address
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* register (a0.x) or predicate register (p0.x) must be serialized. Ie.
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* if you have two pairs of instructions that write the same special
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* register and then read it, then those pairs cannot be interleaved.
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* To solve this, when we are in such a scheduling "critical section",
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* and we encounter a conflicting write to a special register, we try
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* to schedule any remaining instructions that use that value first.
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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*/
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struct ir3_sched_ctx {
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2015-04-30 18:57:15 +01:00
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struct ir3_block *block; /* the current block */
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2015-11-30 20:52:26 +00:00
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struct list_head depth_list; /* depth sorted unscheduled instrs */
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2015-04-30 18:57:15 +01:00
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struct ir3_instruction *scheduled; /* last scheduled instr XXX remove*/
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2014-07-25 14:49:41 +01:00
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struct ir3_instruction *addr; /* current a0.x user, if any */
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2014-07-25 14:50:34 +01:00
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struct ir3_instruction *pred; /* current p0.x user, if any */
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2019-02-27 14:56:18 +00:00
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int live_values; /* estimate of current live values */
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2014-08-29 15:51:40 +01:00
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bool error;
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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};
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2019-08-12 19:34:18 +01:00
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static bool is_scheduled(struct ir3_instruction *instr)
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{
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return !!(instr->flags & IR3_INSTR_MARK);
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}
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2015-04-04 18:37:45 +01:00
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static bool is_sfu_or_mem(struct ir3_instruction *instr)
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{
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return is_sfu(instr) || is_mem(instr);
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}
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2019-02-27 14:56:18 +00:00
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static void
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unuse_each_src(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
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{
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struct ir3_instruction *src;
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foreach_ssa_src_n(src, n, instr) {
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if (__is_false_dep(instr, n))
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continue;
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if (instr->block != src->block)
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continue;
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if ((src->opc == OPC_META_FI) || (src->opc == OPC_META_FO)) {
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unuse_each_src(ctx, src);
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} else {
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debug_assert(src->use_count > 0);
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if (--src->use_count == 0) {
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ctx->live_values -= dest_regs(src);
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debug_assert(ctx->live_values >= 0);
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}
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}
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}
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}
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2019-08-12 19:34:18 +01:00
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static void clear_cache(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr);
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2019-05-24 17:19:55 +01:00
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static void use_instr(struct ir3_instruction *instr);
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2019-08-12 19:34:18 +01:00
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/* transfers a use-count to new instruction, for cases where we
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* "spill" address or predicate. Note this might cause the
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* previous instruction that loaded a0.x/p0.x to become live
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* again, when we previously thought it was dead.
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*/
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static void
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transfer_use(struct ir3_sched_ctx *ctx, struct ir3_instruction *orig_instr,
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struct ir3_instruction *new_instr)
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{
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struct ir3_instruction *src;
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debug_assert(is_scheduled(orig_instr));
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foreach_ssa_src_n(src, n, new_instr) {
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if (__is_false_dep(new_instr, n))
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continue;
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ctx->live_values += dest_regs(src);
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use_instr(src);
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}
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clear_cache(ctx, orig_instr);
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}
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2019-02-27 14:56:18 +00:00
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static void
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use_each_src(struct ir3_instruction *instr)
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{
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struct ir3_instruction *src;
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foreach_ssa_src_n(src, n, instr) {
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if (__is_false_dep(instr, n))
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continue;
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2019-05-24 17:19:55 +01:00
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use_instr(src);
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}
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}
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static void
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use_instr(struct ir3_instruction *instr)
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{
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if ((instr->opc == OPC_META_FI) || (instr->opc == OPC_META_FO)) {
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use_each_src(instr);
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} else {
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instr->use_count++;
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2019-02-27 14:56:18 +00:00
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}
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}
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static void
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update_live_values(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
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{
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if ((instr->opc == OPC_META_FI) || (instr->opc == OPC_META_FO))
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return;
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ctx->live_values += dest_regs(instr);
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unuse_each_src(ctx, instr);
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}
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static void
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2019-05-24 17:19:55 +01:00
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update_use_count(struct ir3 *ir)
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2019-02-27 14:56:18 +00:00
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{
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2019-05-24 17:19:55 +01:00
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list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
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list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
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instr->use_count = 0;
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}
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}
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list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
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list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
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if ((instr->opc == OPC_META_FI) || (instr->opc == OPC_META_FO))
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continue;
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use_each_src(instr);
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}
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2019-02-27 14:56:18 +00:00
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}
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2019-05-24 17:19:55 +01:00
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/* Shader outputs are also used:
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*/
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for (unsigned i = 0; i < ir->noutputs; i++) {
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struct ir3_instruction *out = ir->outputs[i];
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if (!out)
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2019-02-27 14:56:18 +00:00
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continue;
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2019-05-24 17:19:55 +01:00
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use_instr(out);
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2019-02-27 14:56:18 +00:00
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}
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}
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2015-11-30 20:52:26 +00:00
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#define NULL_INSTR ((void *)~0)
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static void
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clear_cache(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
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{
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list_for_each_entry (struct ir3_instruction, instr2, &ctx->depth_list, node) {
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if ((instr2->data == instr) || (instr2->data == NULL_INSTR) || !instr)
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instr2->data = NULL;
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}
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}
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2015-04-30 18:57:15 +01:00
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static void
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schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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|
{
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2015-04-30 18:57:15 +01:00
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debug_assert(ctx->block == instr->block);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
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/* maybe there is a better way to handle this than just stuffing
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* a nop.. ideally we'd know about this constraint in the
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* scheduling and depth calculation..
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*/
|
2015-04-04 18:37:45 +01:00
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if (ctx->scheduled && is_sfu_or_mem(ctx->scheduled) && is_sfu_or_mem(instr))
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2015-04-30 18:57:15 +01:00
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ir3_NOP(ctx->block);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
|
|
|
/* remove from depth list:
|
|
|
|
*/
|
2015-04-30 16:38:43 +01:00
|
|
|
list_delinit(&instr->node);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2014-07-21 20:24:30 +01:00
|
|
|
if (writes_addr(instr)) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->addr == NULL);
|
2014-07-25 14:49:41 +01:00
|
|
|
ctx->addr = instr;
|
2014-07-21 20:24:30 +01:00
|
|
|
}
|
|
|
|
|
2014-07-25 14:50:34 +01:00
|
|
|
if (writes_pred(instr)) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->pred == NULL);
|
2014-07-25 14:50:34 +01:00
|
|
|
ctx->pred = instr;
|
|
|
|
}
|
|
|
|
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
instr->flags |= IR3_INSTR_MARK;
|
|
|
|
|
2015-04-30 16:38:43 +01:00
|
|
|
list_addtail(&instr->node, &instr->block->instr_list);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
ctx->scheduled = instr;
|
2015-11-30 20:52:26 +00:00
|
|
|
|
2019-02-27 14:56:18 +00:00
|
|
|
update_live_values(ctx, instr);
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
if (writes_addr(instr) || writes_pred(instr) || is_input(instr)) {
|
|
|
|
clear_cache(ctx, NULL);
|
|
|
|
} else {
|
|
|
|
/* invalidate only the necessary entries.. */
|
|
|
|
clear_cache(ctx, instr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ir3_instruction *
|
|
|
|
deepest(struct ir3_instruction **srcs, unsigned nsrcs)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *d = NULL;
|
|
|
|
unsigned i = 0, id = 0;
|
|
|
|
|
|
|
|
while ((i < nsrcs) && !(d = srcs[id = i]))
|
|
|
|
i++;
|
|
|
|
|
|
|
|
if (!d)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
for (; i < nsrcs; i++)
|
2019-05-30 18:44:16 +01:00
|
|
|
if (srcs[i] && (srcs[i]->depth > d->depth))
|
2015-11-30 20:52:26 +00:00
|
|
|
d = srcs[id = i];
|
|
|
|
|
|
|
|
srcs[id] = NULL;
|
|
|
|
|
|
|
|
return d;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
2018-02-05 13:45:29 +00:00
|
|
|
/**
|
|
|
|
* @block: the block to search in, starting from end; in first pass,
|
|
|
|
* this will be the block the instruction would be inserted into
|
|
|
|
* (but has not yet, ie. it only contains already scheduled
|
|
|
|
* instructions). For intra-block scheduling (second pass), this
|
|
|
|
* would be one of the predecessor blocks.
|
|
|
|
* @instr: the instruction to search for
|
|
|
|
* @maxd: max distance, bail after searching this # of instruction
|
|
|
|
* slots, since it means the instruction we are looking for is
|
|
|
|
* far enough away
|
|
|
|
* @pred: if true, recursively search into predecessor blocks to
|
|
|
|
* find the worst case (shortest) distance (only possible after
|
|
|
|
* individual blocks are all scheduled
|
|
|
|
*/
|
2015-04-30 18:57:15 +01:00
|
|
|
static unsigned
|
2018-02-05 13:45:29 +00:00
|
|
|
distance(struct ir3_block *block, struct ir3_instruction *instr,
|
|
|
|
unsigned maxd, bool pred)
|
2015-04-30 18:57:15 +01:00
|
|
|
{
|
|
|
|
unsigned d = 0;
|
|
|
|
|
2018-02-05 13:45:29 +00:00
|
|
|
list_for_each_entry_rev (struct ir3_instruction, n, &block->instr_list, node) {
|
2015-04-30 18:57:15 +01:00
|
|
|
if ((n == instr) || (d >= maxd))
|
2018-02-05 13:45:29 +00:00
|
|
|
return d;
|
|
|
|
/* NOTE: don't count branch/jump since we don't know yet if they will
|
|
|
|
* be eliminated later in resolve_jumps().. really should do that
|
|
|
|
* earlier so we don't have this constraint.
|
|
|
|
*/
|
|
|
|
if (is_alu(n) || (is_flow(n) && (n->opc != OPC_JUMP) && (n->opc != OPC_BR)))
|
2015-04-30 18:57:15 +01:00
|
|
|
d++;
|
|
|
|
}
|
|
|
|
|
2018-02-05 13:45:29 +00:00
|
|
|
/* if coming from a predecessor block, assume it is assigned far
|
|
|
|
* enough away.. we'll fix up later.
|
|
|
|
*/
|
|
|
|
if (!pred)
|
|
|
|
return maxd;
|
|
|
|
|
|
|
|
if (pred && (block->data != block)) {
|
|
|
|
/* Search into predecessor blocks, finding the one with the
|
|
|
|
* shortest distance, since that will be the worst case
|
|
|
|
*/
|
|
|
|
unsigned min = maxd - d;
|
|
|
|
|
|
|
|
/* (ab)use block->data to prevent recursion: */
|
|
|
|
block->data = block;
|
|
|
|
|
2019-06-28 15:30:35 +01:00
|
|
|
set_foreach(block->predecessors, entry) {
|
|
|
|
struct ir3_block *pred = (struct ir3_block *)entry->key;
|
2018-02-05 13:45:29 +00:00
|
|
|
unsigned n;
|
|
|
|
|
2019-06-28 15:30:35 +01:00
|
|
|
n = distance(pred, instr, min, pred);
|
2018-02-05 13:45:29 +00:00
|
|
|
|
|
|
|
min = MIN2(min, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
block->data = NULL;
|
|
|
|
d += min;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
return d;
|
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2014-10-18 19:46:35 +01:00
|
|
|
/* calculate delay for specified src: */
|
2015-04-30 18:57:15 +01:00
|
|
|
static unsigned
|
2018-02-05 13:45:29 +00:00
|
|
|
delay_calc_srcn(struct ir3_block *block,
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
struct ir3_instruction *assigner,
|
2018-01-11 21:08:47 +00:00
|
|
|
struct ir3_instruction *consumer,
|
2018-02-05 13:45:29 +00:00
|
|
|
unsigned srcn, bool soft, bool pred)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
|
|
|
unsigned delay = 0;
|
|
|
|
|
|
|
|
if (is_meta(assigner)) {
|
2015-02-02 17:54:25 +00:00
|
|
|
struct ir3_instruction *src;
|
|
|
|
foreach_ssa_src(src, assigner) {
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned d;
|
2018-02-05 13:45:29 +00:00
|
|
|
d = delay_calc_srcn(block, src, consumer, srcn, soft, pred);
|
2015-02-02 17:54:25 +00:00
|
|
|
delay = MAX2(delay, d);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
} else {
|
2018-01-11 21:08:47 +00:00
|
|
|
if (soft) {
|
|
|
|
if (is_sfu(assigner)) {
|
|
|
|
delay = 4;
|
|
|
|
} else {
|
|
|
|
delay = ir3_delayslots(assigner, consumer, srcn);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
delay = ir3_delayslots(assigner, consumer, srcn);
|
|
|
|
}
|
2018-02-05 13:45:29 +00:00
|
|
|
delay -= distance(block, assigner, delay, pred);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2014-10-18 19:46:35 +01:00
|
|
|
/* calculate delay for instruction (maximum of delay for all srcs): */
|
2015-04-30 18:57:15 +01:00
|
|
|
static unsigned
|
2018-02-05 13:45:29 +00:00
|
|
|
delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
|
|
|
|
bool soft, bool pred)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
2015-02-02 17:54:25 +00:00
|
|
|
unsigned delay = 0;
|
|
|
|
struct ir3_instruction *src;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-02-02 17:54:25 +00:00
|
|
|
foreach_ssa_src_n(src, i, instr) {
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned d;
|
2018-02-05 13:45:29 +00:00
|
|
|
d = delay_calc_srcn(block, src, instr, i, soft, pred);
|
2015-02-02 17:54:25 +00:00
|
|
|
delay = MAX2(delay, d);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_sched_notes {
|
|
|
|
/* there is at least one kill which could be scheduled, except
|
|
|
|
* for unscheduled bary.f's:
|
|
|
|
*/
|
|
|
|
bool blocked_kill;
|
|
|
|
/* there is at least one instruction that could be scheduled,
|
|
|
|
* except for conflicting address/predicate register usage:
|
|
|
|
*/
|
|
|
|
bool addr_conflict, pred_conflict;
|
|
|
|
};
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* could an instruction be scheduled if specified ssa src was scheduled? */
|
|
|
|
static bool
|
|
|
|
could_sched(struct ir3_instruction *instr, struct ir3_instruction *src)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *other_src;
|
|
|
|
foreach_ssa_src(other_src, instr) {
|
|
|
|
/* if dependency not scheduled, we aren't ready yet: */
|
|
|
|
if ((src != other_src) && !is_scheduled(other_src)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if instruction is ok to schedule. Make sure it is not blocked
|
|
|
|
* by use of addr/predicate register, etc.
|
|
|
|
*/
|
2015-04-30 18:57:15 +01:00
|
|
|
static bool
|
2015-11-30 20:52:26 +00:00
|
|
|
check_instr(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_instruction *instr)
|
|
|
|
{
|
2019-08-12 19:34:18 +01:00
|
|
|
debug_assert(!is_scheduled(instr));
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* For instructions that write address register we need to
|
|
|
|
* make sure there is at least one instruction that uses the
|
|
|
|
* addr value which is otherwise ready.
|
|
|
|
*
|
|
|
|
* TODO if any instructions use pred register and have other
|
|
|
|
* src args, we would need to do the same for writes_pred()..
|
|
|
|
*/
|
|
|
|
if (writes_addr(instr)) {
|
|
|
|
struct ir3 *ir = instr->block->shader;
|
|
|
|
bool ready = false;
|
|
|
|
for (unsigned i = 0; (i < ir->indirects_count) && !ready; i++) {
|
|
|
|
struct ir3_instruction *indirect = ir->indirects[i];
|
|
|
|
if (!indirect)
|
|
|
|
continue;
|
|
|
|
if (indirect->address != instr)
|
|
|
|
continue;
|
|
|
|
ready = could_sched(indirect, instr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nothing could be scheduled, so keep looking: */
|
|
|
|
if (!ready)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* if this is a write to address/predicate register, and that
|
|
|
|
* register is currently in use, we need to defer until it is
|
|
|
|
* free:
|
|
|
|
*/
|
|
|
|
if (writes_addr(instr) && ctx->addr) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->addr != instr);
|
2015-04-30 18:57:15 +01:00
|
|
|
notes->addr_conflict = true;
|
2015-11-30 20:52:26 +00:00
|
|
|
return false;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (writes_pred(instr) && ctx->pred) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->pred != instr);
|
2015-04-30 18:57:15 +01:00
|
|
|
notes->pred_conflict = true;
|
2015-11-30 20:52:26 +00:00
|
|
|
return false;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
|
|
|
|
2014-10-18 20:28:16 +01:00
|
|
|
/* if the instruction is a kill, we need to ensure *every*
|
|
|
|
* bary.f is scheduled. The hw seems unhappy if the thread
|
|
|
|
* gets killed before the end-input (ei) flag is hit.
|
|
|
|
*
|
|
|
|
* We could do this by adding each bary.f instruction as
|
|
|
|
* virtual ssa src for the kill instruction. But we have
|
|
|
|
* fixed length instr->regs[].
|
|
|
|
*
|
|
|
|
* TODO this wouldn't be quite right if we had multiple
|
|
|
|
* basic blocks, if any block was conditional. We'd need
|
|
|
|
* to schedule the bary.f's outside of any block which
|
|
|
|
* was conditional that contained a kill.. I think..
|
|
|
|
*/
|
|
|
|
if (is_kill(instr)) {
|
|
|
|
struct ir3 *ir = instr->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (unsigned i = 0; i < ir->baryfs_count; i++) {
|
2015-03-11 16:36:26 +00:00
|
|
|
struct ir3_instruction *baryf = ir->baryfs[i];
|
2015-11-26 17:25:18 +00:00
|
|
|
if (baryf->flags & IR3_INSTR_UNUSED)
|
2014-10-18 20:28:16 +01:00
|
|
|
continue;
|
2015-04-30 18:57:15 +01:00
|
|
|
if (!is_scheduled(baryf)) {
|
|
|
|
notes->blocked_kill = true;
|
2015-11-30 20:52:26 +00:00
|
|
|
return false;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
2014-10-18 20:28:16 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
return true;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* Find the best instruction to schedule from specified instruction or
|
|
|
|
* recursively it's ssa sources.
|
|
|
|
*/
|
|
|
|
static struct ir3_instruction *
|
|
|
|
find_instr_recursive(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
|
|
|
struct ir3_instruction *instr)
|
2015-07-02 19:59:08 +01:00
|
|
|
{
|
2015-11-30 20:52:26 +00:00
|
|
|
struct ir3_instruction *srcs[__ssa_src_cnt(instr)];
|
|
|
|
struct ir3_instruction *src;
|
|
|
|
unsigned nsrcs = 0;
|
|
|
|
|
|
|
|
if (is_scheduled(instr))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
/* use instr->data to cache the results of recursing up the
|
|
|
|
* instr src's. Otherwise the recursive algo can scale quite
|
|
|
|
* badly w/ shader size. But this takes some care to clear
|
|
|
|
* the cache appropriately when instructions are scheduled.
|
|
|
|
*/
|
|
|
|
if (instr->data) {
|
|
|
|
if (instr->data == NULL_INSTR)
|
|
|
|
return NULL;
|
|
|
|
return instr->data;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* find unscheduled srcs: */
|
|
|
|
foreach_ssa_src(src, instr) {
|
2019-03-24 15:16:12 +00:00
|
|
|
if (!is_scheduled(src) && (src->block == instr->block)) {
|
2015-11-30 20:52:26 +00:00
|
|
|
debug_assert(nsrcs < ARRAY_SIZE(srcs));
|
|
|
|
srcs[nsrcs++] = src;
|
2015-07-02 19:59:08 +01:00
|
|
|
}
|
|
|
|
}
|
2015-11-30 20:52:26 +00:00
|
|
|
|
|
|
|
/* if all our src's are already scheduled: */
|
|
|
|
if (nsrcs == 0) {
|
|
|
|
if (check_instr(ctx, notes, instr)) {
|
|
|
|
instr->data = instr;
|
|
|
|
return instr;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
while ((src = deepest(srcs, nsrcs))) {
|
|
|
|
struct ir3_instruction *candidate;
|
|
|
|
|
|
|
|
candidate = find_instr_recursive(ctx, notes, src);
|
|
|
|
if (!candidate)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (check_instr(ctx, notes, candidate)) {
|
|
|
|
instr->data = candidate;
|
|
|
|
return candidate;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
instr->data = NULL_INSTR;
|
|
|
|
return NULL;
|
2015-07-02 19:59:08 +01:00
|
|
|
}
|
|
|
|
|
2019-05-30 18:44:16 +01:00
|
|
|
/* find net change to live values if instruction were scheduled: */
|
|
|
|
static int
|
|
|
|
live_effect(struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *src;
|
|
|
|
int new_live = dest_regs(instr);
|
|
|
|
int old_live = 0;
|
|
|
|
|
|
|
|
foreach_ssa_src_n(src, n, instr) {
|
|
|
|
if (__is_false_dep(instr, n))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (instr->block != src->block)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* for fanout/split, just pass things along to the real src: */
|
|
|
|
if (src->opc == OPC_META_FO)
|
|
|
|
src = ssa(src->regs[1]);
|
|
|
|
|
|
|
|
/* for fanin/collect, if this is the last use of *each* src,
|
|
|
|
* then it will decrease the live values, since RA treats
|
|
|
|
* them as a whole:
|
|
|
|
*/
|
|
|
|
if (src->opc == OPC_META_FI) {
|
|
|
|
struct ir3_instruction *src2;
|
|
|
|
bool last_use = true;
|
|
|
|
|
|
|
|
foreach_ssa_src(src2, src) {
|
|
|
|
if (src2->use_count > 1) {
|
|
|
|
last_use = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (last_use)
|
|
|
|
old_live += dest_regs(src);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
debug_assert(src->use_count > 0);
|
|
|
|
|
|
|
|
if (src->use_count == 1) {
|
|
|
|
old_live += dest_regs(src);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return new_live - old_live;
|
|
|
|
}
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* find instruction to schedule: */
|
|
|
|
static struct ir3_instruction *
|
2018-01-11 21:08:47 +00:00
|
|
|
find_eligible_instr(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
|
|
|
bool soft)
|
2014-07-21 20:24:30 +01:00
|
|
|
{
|
2015-11-30 20:52:26 +00:00
|
|
|
struct ir3_instruction *best_instr = NULL;
|
2019-05-30 18:44:16 +01:00
|
|
|
int best_rank = INT_MAX; /* lower is better */
|
|
|
|
unsigned deepest = 0;
|
2015-04-30 18:57:15 +01:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* TODO we'd really rather use the list/array of block outputs. But we
|
|
|
|
* don't have such a thing. Recursing *every* instruction in the list
|
|
|
|
* will result in a lot of repeated traversal, since instructions will
|
|
|
|
* get traversed both when they appear as ssa src to a later instruction
|
|
|
|
* as well as where they appear in the depth_list.
|
|
|
|
*/
|
|
|
|
list_for_each_entry_rev (struct ir3_instruction, instr, &ctx->depth_list, node) {
|
|
|
|
struct ir3_instruction *candidate;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
candidate = find_instr_recursive(ctx, notes, instr);
|
|
|
|
if (!candidate)
|
|
|
|
continue;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
2019-05-28 17:42:26 +01:00
|
|
|
if (is_meta(candidate))
|
|
|
|
return candidate;
|
|
|
|
|
2019-05-30 18:44:16 +01:00
|
|
|
deepest = MAX2(deepest, candidate->depth);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* traverse the list a second time.. but since we cache the result of
|
|
|
|
* find_instr_recursive() it isn't as bad as it looks.
|
|
|
|
*/
|
|
|
|
list_for_each_entry_rev (struct ir3_instruction, instr, &ctx->depth_list, node) {
|
|
|
|
struct ir3_instruction *candidate;
|
|
|
|
|
|
|
|
candidate = find_instr_recursive(ctx, notes, instr);
|
|
|
|
if (!candidate)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* determine net change to # of live values: */
|
|
|
|
int le = live_effect(candidate);
|
|
|
|
|
|
|
|
/* if there is a net increase in # of live values, then apply some
|
|
|
|
* threshold to avoid instructions getting scheduled *too* early
|
|
|
|
* and increasing register pressure.
|
|
|
|
*/
|
|
|
|
if (le >= 1) {
|
|
|
|
unsigned threshold;
|
|
|
|
|
|
|
|
if (ctx->live_values > 4*4) {
|
|
|
|
threshold = 4;
|
|
|
|
} else {
|
|
|
|
threshold = 6;
|
2019-02-27 14:56:18 +00:00
|
|
|
}
|
2019-05-30 18:44:16 +01:00
|
|
|
|
|
|
|
/* Filter out any "shallow" instructions which would otherwise
|
|
|
|
* tend to get scheduled too early to fill delay slots even
|
|
|
|
* when they are not needed for a while. There will probably
|
|
|
|
* be later delay slots that they could just as easily fill.
|
|
|
|
*
|
|
|
|
* A classic case where this comes up is frag shaders that
|
|
|
|
* write a constant value (like 1.0f) to one of the channels
|
|
|
|
* of the output color(s). Since the mov from immed has no
|
|
|
|
* dependencies, it would otherwise get scheduled early to
|
|
|
|
* fill delay slots, occupying a register until the end of
|
|
|
|
* the program.
|
|
|
|
*/
|
|
|
|
if ((deepest - candidate->depth) > threshold)
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
int rank = delay_calc(ctx->block, candidate, soft, false);
|
|
|
|
|
|
|
|
/* if too many live values, prioritize instructions that reduce the
|
|
|
|
* number of live values:
|
|
|
|
*/
|
|
|
|
if (ctx->live_values > 16*4) {
|
|
|
|
rank = le;
|
|
|
|
} else if (ctx->live_values > 4*4) {
|
|
|
|
rank += le;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rank < best_rank) {
|
|
|
|
best_instr = candidate;
|
|
|
|
best_rank = rank;
|
2015-07-02 19:59:08 +01:00
|
|
|
}
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
return best_instr;
|
2014-07-25 14:50:34 +01:00
|
|
|
}
|
|
|
|
|
2019-08-12 19:34:18 +01:00
|
|
|
static struct ir3_instruction *
|
|
|
|
split_instr(struct ir3_sched_ctx *ctx, struct ir3_instruction *orig_instr)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *new_instr = ir3_instr_clone(orig_instr);
|
|
|
|
ir3_insert_by_depth(new_instr, &ctx->depth_list);
|
|
|
|
transfer_use(ctx, orig_instr, new_instr);
|
|
|
|
return new_instr;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* "spill" the address register by remapping any unscheduled
|
|
|
|
* instructions which depend on the current address register
|
|
|
|
* to a clone of the instruction which wrote the address reg.
|
2014-07-21 20:24:30 +01:00
|
|
|
*/
|
2015-07-02 19:59:08 +01:00
|
|
|
static struct ir3_instruction *
|
2015-04-30 18:57:15 +01:00
|
|
|
split_addr(struct ir3_sched_ctx *ctx)
|
2014-07-21 20:24:30 +01:00
|
|
|
{
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3 *ir;
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_instruction *new_addr = NULL;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
debug_assert(ctx->addr);
|
|
|
|
|
2015-07-02 19:59:08 +01:00
|
|
|
ir = ctx->addr->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (i = 0; i < ir->indirects_count; i++) {
|
|
|
|
struct ir3_instruction *indirect = ir->indirects[i];
|
|
|
|
|
2015-07-02 20:38:34 +01:00
|
|
|
if (!indirect)
|
|
|
|
continue;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* skip instructions already scheduled: */
|
2015-07-02 19:59:08 +01:00
|
|
|
if (is_scheduled(indirect))
|
2015-04-30 18:57:15 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* remap remaining instructions using current addr
|
|
|
|
* to new addr:
|
|
|
|
*/
|
|
|
|
if (indirect->address == ctx->addr) {
|
|
|
|
if (!new_addr) {
|
2019-08-12 19:34:18 +01:00
|
|
|
new_addr = split_instr(ctx, ctx->addr);
|
2015-04-30 18:57:15 +01:00
|
|
|
/* original addr is scheduled, but new one isn't: */
|
|
|
|
new_addr->flags &= ~IR3_INSTR_MARK;
|
|
|
|
}
|
2019-09-02 18:08:37 +01:00
|
|
|
indirect->address = NULL;
|
2015-07-02 18:52:38 +01:00
|
|
|
ir3_instr_set_address(indirect, new_addr);
|
2014-07-21 20:24:30 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* all remaining indirects remapped to new addr: */
|
|
|
|
ctx->addr = NULL;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
return new_addr;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* "spill" the predicate register by remapping any unscheduled
|
|
|
|
* instructions which depend on the current predicate register
|
|
|
|
* to a clone of the instruction which wrote the address reg.
|
|
|
|
*/
|
2015-07-02 19:59:08 +01:00
|
|
|
static struct ir3_instruction *
|
2015-04-30 18:57:15 +01:00
|
|
|
split_pred(struct ir3_sched_ctx *ctx)
|
|
|
|
{
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3 *ir;
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_instruction *new_pred = NULL;
|
|
|
|
unsigned i;
|
2014-07-25 14:50:34 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
debug_assert(ctx->pred);
|
2015-04-08 16:04:37 +01:00
|
|
|
|
2015-07-02 19:59:08 +01:00
|
|
|
ir = ctx->pred->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (i = 0; i < ir->predicates_count; i++) {
|
|
|
|
struct ir3_instruction *predicated = ir->predicates[i];
|
2015-04-08 16:04:37 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* skip instructions already scheduled: */
|
2015-07-02 19:59:08 +01:00
|
|
|
if (is_scheduled(predicated))
|
2015-04-30 18:57:15 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* remap remaining instructions using current pred
|
|
|
|
* to new pred:
|
|
|
|
*
|
|
|
|
* TODO is there ever a case when pred isn't first
|
|
|
|
* (and only) src?
|
|
|
|
*/
|
|
|
|
if (ssa(predicated->regs[1]) == ctx->pred) {
|
|
|
|
if (!new_pred) {
|
2019-08-12 19:34:18 +01:00
|
|
|
new_pred = split_instr(ctx, ctx->pred);
|
2015-04-30 18:57:15 +01:00
|
|
|
/* original pred is scheduled, but new one isn't: */
|
|
|
|
new_pred->flags &= ~IR3_INSTR_MARK;
|
|
|
|
}
|
|
|
|
predicated->regs[1]->instr = new_pred;
|
2015-04-08 16:04:37 +01:00
|
|
|
}
|
|
|
|
}
|
2014-08-29 15:51:40 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* all remaining predicated remapped to new pred: */
|
|
|
|
ctx->pred = NULL;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
return new_pred;
|
2014-07-21 20:24:30 +01:00
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
static void
|
|
|
|
sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
2015-11-30 20:52:26 +00:00
|
|
|
struct list_head unscheduled_list;
|
2015-04-30 16:38:43 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
ctx->block = block;
|
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* addr/pred writes are per-block: */
|
|
|
|
ctx->addr = NULL;
|
|
|
|
ctx->pred = NULL;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* move all instructions to the unscheduled list, and
|
|
|
|
* empty the block's instruction list (to which we will
|
2015-11-30 20:52:26 +00:00
|
|
|
* be inserting).
|
2015-04-30 18:57:15 +01:00
|
|
|
*/
|
2015-04-30 16:38:43 +01:00
|
|
|
list_replace(&block->instr_list, &unscheduled_list);
|
|
|
|
list_inithead(&block->instr_list);
|
2015-11-30 20:52:26 +00:00
|
|
|
list_inithead(&ctx->depth_list);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2018-01-29 21:22:26 +00:00
|
|
|
/* first a pre-pass to schedule all meta:input instructions
|
2015-04-30 18:57:15 +01:00
|
|
|
* (which need to appear first so that RA knows the register is
|
2015-11-30 20:52:26 +00:00
|
|
|
* occupied), and move remaining to depth sorted list:
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
*/
|
2015-04-30 16:38:43 +01:00
|
|
|
list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) {
|
2019-10-11 23:57:22 +01:00
|
|
|
if ((instr->opc == OPC_META_INPUT) ||
|
|
|
|
(instr->opc == OPC_META_TEX_PREFETCH)) {
|
2015-04-30 18:57:15 +01:00
|
|
|
schedule(ctx, instr);
|
2015-11-30 20:52:26 +00:00
|
|
|
} else {
|
|
|
|
ir3_insert_by_depth(instr, &ctx->depth_list);
|
|
|
|
}
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
while (!list_empty(&ctx->depth_list)) {
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_sched_notes notes = {0};
|
2015-11-30 20:52:26 +00:00
|
|
|
struct ir3_instruction *instr;
|
|
|
|
|
2018-01-11 21:08:47 +00:00
|
|
|
instr = find_eligible_instr(ctx, ¬es, true);
|
|
|
|
if (!instr)
|
|
|
|
instr = find_eligible_instr(ctx, ¬es, false);
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
if (instr) {
|
2018-02-05 13:45:29 +00:00
|
|
|
unsigned delay = delay_calc(ctx->block, instr, false, false);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-11-30 20:52:26 +00:00
|
|
|
/* and if we run out of instructions that can be scheduled,
|
|
|
|
* then it is time for nop's:
|
2015-04-30 18:57:15 +01:00
|
|
|
*/
|
2015-11-30 20:52:26 +00:00
|
|
|
debug_assert(delay <= 6);
|
|
|
|
while (delay > 0) {
|
|
|
|
ir3_NOP(block);
|
|
|
|
delay--;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
schedule(ctx, instr);
|
2015-11-30 20:52:26 +00:00
|
|
|
} else {
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3_instruction *new_instr = NULL;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* nothing available to schedule.. if we are blocked on
|
|
|
|
* address/predicate register conflict, then break the
|
|
|
|
* deadlock by cloning the instruction that wrote that
|
|
|
|
* reg:
|
|
|
|
*/
|
|
|
|
if (notes.addr_conflict) {
|
2015-07-02 19:59:08 +01:00
|
|
|
new_instr = split_addr(ctx);
|
2015-04-30 18:57:15 +01:00
|
|
|
} else if (notes.pred_conflict) {
|
2015-07-02 19:59:08 +01:00
|
|
|
new_instr = split_pred(ctx);
|
2015-04-30 18:57:15 +01:00
|
|
|
} else {
|
|
|
|
debug_assert(0);
|
|
|
|
ctx->error = true;
|
|
|
|
return;
|
|
|
|
}
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
if (new_instr) {
|
2015-11-30 20:52:26 +00:00
|
|
|
/* clearing current addr/pred can change what is
|
|
|
|
* available to schedule, so clear cache..
|
|
|
|
*/
|
|
|
|
clear_cache(ctx, NULL);
|
|
|
|
|
|
|
|
ir3_insert_by_depth(new_instr, &ctx->depth_list);
|
2015-07-06 01:17:56 +01:00
|
|
|
/* the original instr that wrote addr/pred may have
|
|
|
|
* originated from a different block:
|
|
|
|
*/
|
|
|
|
new_instr->block = block;
|
2015-07-02 19:59:08 +01:00
|
|
|
}
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
2015-06-09 22:17:06 +01:00
|
|
|
|
|
|
|
/* And lastly, insert branch/jump instructions to take us to
|
|
|
|
* the next block. Later we'll strip back out the branches
|
|
|
|
* that simply jump to next instruction.
|
|
|
|
*/
|
|
|
|
if (block->successors[1]) {
|
|
|
|
/* if/else, conditional branches to "then" or "else": */
|
|
|
|
struct ir3_instruction *br;
|
|
|
|
unsigned delay = 6;
|
|
|
|
|
|
|
|
debug_assert(ctx->pred);
|
|
|
|
debug_assert(block->condition);
|
|
|
|
|
2018-02-05 13:45:29 +00:00
|
|
|
delay -= distance(ctx->block, ctx->pred, delay, false);
|
2015-06-09 22:17:06 +01:00
|
|
|
|
|
|
|
while (delay > 0) {
|
|
|
|
ir3_NOP(block);
|
|
|
|
delay--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* create "else" branch first (since "then" block should
|
|
|
|
* frequently/always end up being a fall-thru):
|
|
|
|
*/
|
|
|
|
br = ir3_BR(block);
|
|
|
|
br->cat0.inv = true;
|
|
|
|
br->cat0.target = block->successors[1];
|
|
|
|
|
|
|
|
/* NOTE: we have to hard code delay of 6 above, since
|
|
|
|
* we want to insert the nop's before constructing the
|
|
|
|
* branch. Throw in an assert so we notice if this
|
|
|
|
* ever breaks on future generation:
|
|
|
|
*/
|
|
|
|
debug_assert(ir3_delayslots(ctx->pred, br, 0) == 6);
|
|
|
|
|
|
|
|
br = ir3_BR(block);
|
|
|
|
br->cat0.target = block->successors[0];
|
|
|
|
|
|
|
|
} else if (block->successors[0]) {
|
|
|
|
/* otherwise unconditional jump to next block: */
|
|
|
|
struct ir3_instruction *jmp;
|
|
|
|
|
|
|
|
jmp = ir3_JUMP(block);
|
|
|
|
jmp->cat0.target = block->successors[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTE: if we kept track of the predecessors, we could do a better
|
|
|
|
* job w/ (jp) flags.. every node w/ > predecessor is a join point.
|
|
|
|
* Note that as we eliminate blocks which contain only an unconditional
|
|
|
|
* jump we probably need to propagate (jp) flag..
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2018-02-05 13:45:29 +00:00
|
|
|
/* After scheduling individual blocks, we still could have cases where
|
|
|
|
* one (or more) paths into a block, a value produced by a previous
|
|
|
|
* has too few delay slots to be legal. We can't deal with this in the
|
|
|
|
* first pass, because loops (ie. we can't ensure all predecessor blocks
|
|
|
|
* are already scheduled in the first pass). All we can really do at
|
|
|
|
* this point is stuff in extra nop's until things are legal.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
sched_intra_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
|
|
|
{
|
|
|
|
unsigned n = 0;
|
|
|
|
|
|
|
|
ctx->block = block;
|
|
|
|
|
|
|
|
list_for_each_entry_safe (struct ir3_instruction, instr, &block->instr_list, node) {
|
|
|
|
unsigned delay = 0;
|
|
|
|
|
2019-06-28 15:30:35 +01:00
|
|
|
set_foreach(block->predecessors, entry) {
|
|
|
|
struct ir3_block *pred = (struct ir3_block *)entry->key;
|
|
|
|
unsigned d = delay_calc(pred, instr, false, true);
|
2018-02-05 13:45:29 +00:00
|
|
|
delay = MAX2(d, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
while (delay > n) {
|
|
|
|
struct ir3_instruction *nop = ir3_NOP(block);
|
|
|
|
|
|
|
|
/* move to before instr: */
|
|
|
|
list_delinit(&nop->node);
|
|
|
|
list_addtail(&nop->node, &instr->node);
|
|
|
|
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we can bail once we hit worst case delay: */
|
|
|
|
if (++n > 6)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-25 15:30:54 +01:00
|
|
|
int ir3_sched(struct ir3 *ir)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
|
|
|
struct ir3_sched_ctx ctx = {0};
|
2018-01-29 21:22:26 +00:00
|
|
|
|
2015-06-09 22:17:06 +01:00
|
|
|
ir3_clear_mark(ir);
|
2019-05-24 17:19:55 +01:00
|
|
|
update_use_count(ir);
|
2018-02-05 13:45:29 +00:00
|
|
|
|
2015-06-09 22:17:06 +01:00
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
2019-02-27 14:56:18 +00:00
|
|
|
ctx.live_values = 0;
|
2015-06-09 22:17:06 +01:00
|
|
|
sched_block(&ctx, block);
|
|
|
|
}
|
2018-02-05 13:45:29 +00:00
|
|
|
|
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
|
|
|
sched_intra_block(&ctx, block);
|
|
|
|
}
|
|
|
|
|
2014-08-29 15:51:40 +01:00
|
|
|
if (ctx.error)
|
|
|
|
return -1;
|
2019-02-27 14:56:18 +00:00
|
|
|
|
2014-08-29 15:51:40 +01:00
|
|
|
return 0;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
2017-11-07 20:12:03 +00:00
|
|
|
|
2019-03-26 19:21:12 +00:00
|
|
|
static unsigned
|
|
|
|
get_array_id(struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
/* The expectation is that there is only a single array
|
|
|
|
* src or dst, ir3_cp should enforce this.
|
|
|
|
*/
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < instr->regs_count; i++)
|
|
|
|
if (instr->regs[i]->flags & IR3_REG_ARRAY)
|
|
|
|
return instr->regs[i]->array.id;
|
|
|
|
|
|
|
|
unreachable("this was unexpected");
|
|
|
|
}
|
|
|
|
|
2017-11-07 20:12:03 +00:00
|
|
|
/* does instruction 'prior' need to be scheduled before 'instr'? */
|
|
|
|
static bool
|
|
|
|
depends_on(struct ir3_instruction *instr, struct ir3_instruction *prior)
|
|
|
|
{
|
|
|
|
/* TODO for dependencies that are related to a specific object, ie
|
|
|
|
* a specific SSBO/image/array, we could relax this constraint to
|
|
|
|
* make accesses to unrelated objects not depend on each other (at
|
|
|
|
* least as long as not declared coherent)
|
|
|
|
*/
|
2017-12-03 16:50:09 +00:00
|
|
|
if (((instr->barrier_class & IR3_BARRIER_EVERYTHING) && prior->barrier_class) ||
|
|
|
|
((prior->barrier_class & IR3_BARRIER_EVERYTHING) && instr->barrier_class))
|
2017-11-07 20:12:03 +00:00
|
|
|
return true;
|
2019-03-26 19:21:12 +00:00
|
|
|
|
|
|
|
if (instr->barrier_class & prior->barrier_conflict) {
|
|
|
|
if (!(instr->barrier_class & ~(IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W))) {
|
|
|
|
/* if only array barrier, then we can further limit false-deps
|
|
|
|
* by considering the array-id, ie reads/writes to different
|
|
|
|
* arrays do not depend on each other (no aliasing)
|
|
|
|
*/
|
|
|
|
if (get_array_id(instr) != get_array_id(prior)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
2017-11-07 20:12:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
add_barrier_deps(struct ir3_block *block, struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
struct list_head *prev = instr->node.prev;
|
|
|
|
struct list_head *next = instr->node.next;
|
|
|
|
|
|
|
|
/* add dependencies on previous instructions that must be scheduled
|
|
|
|
* prior to the current instruction
|
|
|
|
*/
|
|
|
|
while (prev != &block->instr_list) {
|
|
|
|
struct ir3_instruction *pi =
|
|
|
|
LIST_ENTRY(struct ir3_instruction, prev, node);
|
|
|
|
|
|
|
|
prev = prev->prev;
|
|
|
|
|
|
|
|
if (is_meta(pi))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (instr->barrier_class == pi->barrier_class) {
|
|
|
|
ir3_instr_add_dep(instr, pi);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (depends_on(instr, pi))
|
|
|
|
ir3_instr_add_dep(instr, pi);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add dependencies on this instruction to following instructions
|
|
|
|
* that must be scheduled after the current instruction:
|
|
|
|
*/
|
|
|
|
while (next != &block->instr_list) {
|
|
|
|
struct ir3_instruction *ni =
|
|
|
|
LIST_ENTRY(struct ir3_instruction, next, node);
|
|
|
|
|
|
|
|
next = next->next;
|
|
|
|
|
|
|
|
if (is_meta(ni))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (instr->barrier_class == ni->barrier_class) {
|
|
|
|
ir3_instr_add_dep(ni, instr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (depends_on(ni, instr))
|
|
|
|
ir3_instr_add_dep(ni, instr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* before scheduling a block, we need to add any necessary false-dependencies
|
|
|
|
* to ensure that:
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*
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* (1) barriers are scheduled in the right order wrt instructions related
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* to the barrier
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*
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* (2) reads that come before a write actually get scheduled before the
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* write
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*/
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static void
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calculate_deps(struct ir3_block *block)
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{
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list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
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if (instr->barrier_class) {
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add_barrier_deps(block, instr);
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}
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}
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}
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void
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ir3_sched_add_deps(struct ir3 *ir)
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{
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list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
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calculate_deps(block);
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}
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}
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