freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
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/*
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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "util/u_math.h"
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#include "ir3.h"
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/*
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* Instruction Scheduling:
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*
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2015-04-30 18:57:15 +01:00
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* A priority-queue based scheduling algo. Add eligible instructions,
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* ie. ones with all their dependencies scheduled, to the priority
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* (depth) sorted queue (list). Pop highest priority instruction off
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* the queue and schedule it, add newly eligible instructions to the
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* priority queue, rinse, repeat.
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2014-07-25 14:50:34 +01:00
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*
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* There are a few special cases that need to be handled, since sched
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* is currently independent of register allocation. Usages of address
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* register (a0.x) or predicate register (p0.x) must be serialized. Ie.
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* if you have two pairs of instructions that write the same special
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* register and then read it, then those pairs cannot be interleaved.
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* To solve this, when we are in such a scheduling "critical section",
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* and we encounter a conflicting write to a special register, we try
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* to schedule any remaining instructions that use that value first.
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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*/
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struct ir3_sched_ctx {
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2015-04-30 18:57:15 +01:00
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struct ir3_block *block; /* the current block */
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struct ir3_instruction *scheduled; /* last scheduled instr XXX remove*/
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2014-07-25 14:49:41 +01:00
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struct ir3_instruction *addr; /* current a0.x user, if any */
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2014-07-25 14:50:34 +01:00
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struct ir3_instruction *pred; /* current p0.x user, if any */
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2014-08-29 15:51:40 +01:00
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bool error;
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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};
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2015-04-04 18:37:45 +01:00
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static bool is_sfu_or_mem(struct ir3_instruction *instr)
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{
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return is_sfu(instr) || is_mem(instr);
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}
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2015-04-30 18:57:15 +01:00
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static void
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schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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{
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2015-04-30 18:57:15 +01:00
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debug_assert(ctx->block == instr->block);
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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/* maybe there is a better way to handle this than just stuffing
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* a nop.. ideally we'd know about this constraint in the
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* scheduling and depth calculation..
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*/
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2015-04-04 18:37:45 +01:00
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if (ctx->scheduled && is_sfu_or_mem(ctx->scheduled) && is_sfu_or_mem(instr))
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2015-04-30 18:57:15 +01:00
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ir3_NOP(ctx->block);
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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/* remove from depth list:
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*/
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2015-04-30 16:38:43 +01:00
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list_delinit(&instr->node);
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
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2014-07-21 20:24:30 +01:00
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if (writes_addr(instr)) {
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2015-07-02 19:59:08 +01:00
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debug_assert(ctx->addr == NULL);
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2014-07-25 14:49:41 +01:00
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ctx->addr = instr;
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2014-07-21 20:24:30 +01:00
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}
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2014-07-25 14:50:34 +01:00
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if (writes_pred(instr)) {
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2015-07-02 19:59:08 +01:00
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debug_assert(ctx->pred == NULL);
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2014-07-25 14:50:34 +01:00
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ctx->pred = instr;
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}
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
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instr->flags |= IR3_INSTR_MARK;
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2015-04-30 16:38:43 +01:00
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list_addtail(&instr->node, &instr->block->instr_list);
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freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
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ctx->scheduled = instr;
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}
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2015-04-30 18:57:15 +01:00
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static unsigned
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distance(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr,
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unsigned maxd)
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{
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struct list_head *instr_list = &ctx->block->instr_list;
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unsigned d = 0;
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list_for_each_entry_rev (struct ir3_instruction, n, instr_list, node) {
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if ((n == instr) || (d >= maxd))
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break;
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|
if (is_alu(n) || is_flow(n))
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d++;
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}
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|
|
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return d;
|
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2014-10-18 19:46:35 +01:00
|
|
|
/* calculate delay for specified src: */
|
2015-04-30 18:57:15 +01:00
|
|
|
static unsigned
|
|
|
|
delay_calc_srcn(struct ir3_sched_ctx *ctx,
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
struct ir3_instruction *assigner,
|
|
|
|
struct ir3_instruction *consumer, unsigned srcn)
|
|
|
|
{
|
|
|
|
unsigned delay = 0;
|
|
|
|
|
|
|
|
if (is_meta(assigner)) {
|
2015-02-02 17:54:25 +00:00
|
|
|
struct ir3_instruction *src;
|
|
|
|
foreach_ssa_src(src, assigner) {
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned d;
|
|
|
|
if (src->block != assigner->block)
|
|
|
|
break;
|
|
|
|
d = delay_calc_srcn(ctx, src, consumer, srcn);
|
2015-02-02 17:54:25 +00:00
|
|
|
delay = MAX2(delay, d);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
delay = ir3_delayslots(assigner, consumer, srcn);
|
|
|
|
delay -= distance(ctx, assigner, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2014-10-18 19:46:35 +01:00
|
|
|
/* calculate delay for instruction (maximum of delay for all srcs): */
|
2015-04-30 18:57:15 +01:00
|
|
|
static unsigned
|
|
|
|
delay_calc(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
2015-02-02 17:54:25 +00:00
|
|
|
unsigned delay = 0;
|
|
|
|
struct ir3_instruction *src;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-02-02 17:54:25 +00:00
|
|
|
foreach_ssa_src_n(src, i, instr) {
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned d;
|
|
|
|
if (src->block != instr->block)
|
|
|
|
continue;
|
|
|
|
d = delay_calc_srcn(ctx, src, instr, i);
|
2015-02-02 17:54:25 +00:00
|
|
|
delay = MAX2(delay, d);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_sched_notes {
|
|
|
|
/* there is at least one kill which could be scheduled, except
|
|
|
|
* for unscheduled bary.f's:
|
|
|
|
*/
|
|
|
|
bool blocked_kill;
|
|
|
|
/* there is at least one instruction that could be scheduled,
|
|
|
|
* except for conflicting address/predicate register usage:
|
|
|
|
*/
|
|
|
|
bool addr_conflict, pred_conflict;
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool is_scheduled(struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
return !!(instr->flags & IR3_INSTR_MARK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
check_conflict(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
|
|
|
struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
/* if this is a write to address/predicate register, and that
|
|
|
|
* register is currently in use, we need to defer until it is
|
|
|
|
* free:
|
|
|
|
*/
|
|
|
|
if (writes_addr(instr) && ctx->addr) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->addr != instr);
|
2015-04-30 18:57:15 +01:00
|
|
|
notes->addr_conflict = true;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (writes_pred(instr) && ctx->pred) {
|
2015-07-02 19:59:08 +01:00
|
|
|
debug_assert(ctx->pred != instr);
|
2015-04-30 18:57:15 +01:00
|
|
|
notes->pred_conflict = true;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* is this instruction ready to be scheduled? Return negative for not
|
|
|
|
* ready (updating notes if needed), or >= 0 to indicate number of
|
|
|
|
* delay slots needed.
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
*/
|
2015-04-30 18:57:15 +01:00
|
|
|
static int
|
|
|
|
instr_eligibility(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
struct ir3_instruction *instr)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *src;
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned delay = 0;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-06-09 22:17:06 +01:00
|
|
|
/* Phi instructions can have a dependency on something not
|
|
|
|
* scheduled yet (for ex, loops). But OTOH we don't really
|
|
|
|
* care. By definition phi's should appear at the top of
|
|
|
|
* the block, and it's sources should be values from the
|
|
|
|
* previously executing block, so they are always ready to
|
|
|
|
* be scheduled:
|
|
|
|
*/
|
|
|
|
if (is_meta(instr) && (instr->opc == OPC_META_PHI))
|
|
|
|
return 0;
|
|
|
|
|
2015-02-02 17:54:25 +00:00
|
|
|
foreach_ssa_src(src, instr) {
|
2015-04-30 18:57:15 +01:00
|
|
|
/* if dependency not scheduled, we aren't ready yet: */
|
|
|
|
if (!is_scheduled(src))
|
|
|
|
return -1;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* all our dependents are scheduled, figure out if
|
|
|
|
* we have enough delay slots to schedule ourself:
|
|
|
|
*/
|
|
|
|
delay = delay_calc(ctx, instr);
|
2014-07-21 20:24:30 +01:00
|
|
|
if (delay)
|
|
|
|
return delay;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2014-10-18 20:28:16 +01:00
|
|
|
/* if the instruction is a kill, we need to ensure *every*
|
|
|
|
* bary.f is scheduled. The hw seems unhappy if the thread
|
|
|
|
* gets killed before the end-input (ei) flag is hit.
|
|
|
|
*
|
|
|
|
* We could do this by adding each bary.f instruction as
|
|
|
|
* virtual ssa src for the kill instruction. But we have
|
|
|
|
* fixed length instr->regs[].
|
|
|
|
*
|
|
|
|
* TODO this wouldn't be quite right if we had multiple
|
|
|
|
* basic blocks, if any block was conditional. We'd need
|
|
|
|
* to schedule the bary.f's outside of any block which
|
|
|
|
* was conditional that contained a kill.. I think..
|
|
|
|
*/
|
|
|
|
if (is_kill(instr)) {
|
|
|
|
struct ir3 *ir = instr->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (unsigned i = 0; i < ir->baryfs_count; i++) {
|
2015-03-11 16:36:26 +00:00
|
|
|
struct ir3_instruction *baryf = ir->baryfs[i];
|
2015-11-26 17:25:18 +00:00
|
|
|
if (baryf->flags & IR3_INSTR_UNUSED)
|
2014-10-18 20:28:16 +01:00
|
|
|
continue;
|
2015-04-30 18:57:15 +01:00
|
|
|
if (!is_scheduled(baryf)) {
|
|
|
|
notes->blocked_kill = true;
|
|
|
|
return -1;
|
|
|
|
}
|
2014-10-18 20:28:16 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
if (check_conflict(ctx, notes, instr))
|
|
|
|
return -1;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
return 0;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
2015-07-02 19:59:08 +01:00
|
|
|
/* could an instruction be scheduled if specified ssa src was scheduled? */
|
|
|
|
static bool
|
|
|
|
could_sched(struct ir3_instruction *instr, struct ir3_instruction *src)
|
|
|
|
{
|
|
|
|
struct ir3_instruction *other_src;
|
|
|
|
foreach_ssa_src(other_src, instr) {
|
|
|
|
/* if dependency not scheduled, we aren't ready yet: */
|
|
|
|
if ((src != other_src) && !is_scheduled(other_src)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* move eligible instructions to the priority list: */
|
|
|
|
static unsigned
|
|
|
|
add_eligible_instrs(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
|
|
|
struct list_head *prio_queue, struct list_head *unscheduled_list)
|
2014-07-21 20:24:30 +01:00
|
|
|
{
|
2015-04-30 18:57:15 +01:00
|
|
|
unsigned min_delay = ~0;
|
|
|
|
|
|
|
|
list_for_each_entry_safe (struct ir3_instruction, instr, unscheduled_list, node) {
|
|
|
|
int e = instr_eligibility(ctx, notes, instr);
|
|
|
|
if (e < 0)
|
|
|
|
continue;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
/* For instructions that write address register we need to
|
|
|
|
* make sure there is at least one instruction that uses the
|
|
|
|
* addr value which is otherwise ready.
|
|
|
|
*
|
|
|
|
* TODO if any instructions use pred register and have other
|
|
|
|
* src args, we would need to do the same for writes_pred()..
|
|
|
|
*/
|
|
|
|
if (unlikely(writes_addr(instr))) {
|
|
|
|
struct ir3 *ir = instr->block->shader;
|
|
|
|
bool ready = false;
|
|
|
|
for (unsigned i = 0; (i < ir->indirects_count) && !ready; i++) {
|
|
|
|
struct ir3_instruction *indirect = ir->indirects[i];
|
2015-07-02 20:38:34 +01:00
|
|
|
if (!indirect)
|
|
|
|
continue;
|
2015-07-02 19:59:08 +01:00
|
|
|
if (indirect->address != instr)
|
|
|
|
continue;
|
|
|
|
ready = could_sched(indirect, instr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nothing could be scheduled, so keep looking: */
|
|
|
|
if (!ready)
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
min_delay = MIN2(min_delay, e);
|
|
|
|
if (e == 0) {
|
|
|
|
/* remove from unscheduled list and into priority queue: */
|
|
|
|
list_delinit(&instr->node);
|
|
|
|
ir3_insert_by_depth(instr, prio_queue);
|
|
|
|
}
|
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
return min_delay;
|
2014-07-25 14:50:34 +01:00
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* "spill" the address register by remapping any unscheduled
|
|
|
|
* instructions which depend on the current address register
|
|
|
|
* to a clone of the instruction which wrote the address reg.
|
2014-07-21 20:24:30 +01:00
|
|
|
*/
|
2015-07-02 19:59:08 +01:00
|
|
|
static struct ir3_instruction *
|
2015-04-30 18:57:15 +01:00
|
|
|
split_addr(struct ir3_sched_ctx *ctx)
|
2014-07-21 20:24:30 +01:00
|
|
|
{
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3 *ir;
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_instruction *new_addr = NULL;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
debug_assert(ctx->addr);
|
|
|
|
|
2015-07-02 19:59:08 +01:00
|
|
|
ir = ctx->addr->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (i = 0; i < ir->indirects_count; i++) {
|
|
|
|
struct ir3_instruction *indirect = ir->indirects[i];
|
|
|
|
|
2015-07-02 20:38:34 +01:00
|
|
|
if (!indirect)
|
|
|
|
continue;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* skip instructions already scheduled: */
|
2015-07-02 19:59:08 +01:00
|
|
|
if (is_scheduled(indirect))
|
2015-04-30 18:57:15 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* remap remaining instructions using current addr
|
|
|
|
* to new addr:
|
|
|
|
*/
|
|
|
|
if (indirect->address == ctx->addr) {
|
|
|
|
if (!new_addr) {
|
|
|
|
new_addr = ir3_instr_clone(ctx->addr);
|
|
|
|
/* original addr is scheduled, but new one isn't: */
|
|
|
|
new_addr->flags &= ~IR3_INSTR_MARK;
|
|
|
|
}
|
2015-07-02 18:52:38 +01:00
|
|
|
ir3_instr_set_address(indirect, new_addr);
|
2014-07-21 20:24:30 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* all remaining indirects remapped to new addr: */
|
|
|
|
ctx->addr = NULL;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
return new_addr;
|
2015-04-30 18:57:15 +01:00
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* "spill" the predicate register by remapping any unscheduled
|
|
|
|
* instructions which depend on the current predicate register
|
|
|
|
* to a clone of the instruction which wrote the address reg.
|
|
|
|
*/
|
2015-07-02 19:59:08 +01:00
|
|
|
static struct ir3_instruction *
|
2015-04-30 18:57:15 +01:00
|
|
|
split_pred(struct ir3_sched_ctx *ctx)
|
|
|
|
{
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3 *ir;
|
2015-04-30 18:57:15 +01:00
|
|
|
struct ir3_instruction *new_pred = NULL;
|
|
|
|
unsigned i;
|
2014-07-25 14:50:34 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
debug_assert(ctx->pred);
|
2015-04-08 16:04:37 +01:00
|
|
|
|
2015-07-02 19:59:08 +01:00
|
|
|
ir = ctx->pred->block->shader;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
for (i = 0; i < ir->predicates_count; i++) {
|
|
|
|
struct ir3_instruction *predicated = ir->predicates[i];
|
2015-04-08 16:04:37 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* skip instructions already scheduled: */
|
2015-07-02 19:59:08 +01:00
|
|
|
if (is_scheduled(predicated))
|
2015-04-30 18:57:15 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* remap remaining instructions using current pred
|
|
|
|
* to new pred:
|
|
|
|
*
|
|
|
|
* TODO is there ever a case when pred isn't first
|
|
|
|
* (and only) src?
|
|
|
|
*/
|
|
|
|
if (ssa(predicated->regs[1]) == ctx->pred) {
|
|
|
|
if (!new_pred) {
|
|
|
|
new_pred = ir3_instr_clone(ctx->pred);
|
|
|
|
/* original pred is scheduled, but new one isn't: */
|
|
|
|
new_pred->flags &= ~IR3_INSTR_MARK;
|
|
|
|
}
|
|
|
|
predicated->regs[1]->instr = new_pred;
|
2015-04-08 16:04:37 +01:00
|
|
|
}
|
|
|
|
}
|
2014-08-29 15:51:40 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* all remaining predicated remapped to new pred: */
|
|
|
|
ctx->pred = NULL;
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
return new_pred;
|
2014-07-21 20:24:30 +01:00
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
static void
|
|
|
|
sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
2015-04-30 18:57:15 +01:00
|
|
|
struct list_head unscheduled_list, prio_queue;
|
2015-04-30 16:38:43 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
ctx->block = block;
|
|
|
|
|
|
|
|
/* move all instructions to the unscheduled list, and
|
|
|
|
* empty the block's instruction list (to which we will
|
|
|
|
* be inserting.
|
|
|
|
*/
|
2015-04-30 16:38:43 +01:00
|
|
|
list_replace(&block->instr_list, &unscheduled_list);
|
|
|
|
list_inithead(&block->instr_list);
|
2015-04-30 18:57:15 +01:00
|
|
|
list_inithead(&prio_queue);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* first a pre-pass to schedule all meta:input/phi instructions
|
|
|
|
* (which need to appear first so that RA knows the register is
|
|
|
|
* occupied:
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
*/
|
2015-04-30 16:38:43 +01:00
|
|
|
list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) {
|
2015-04-30 18:57:15 +01:00
|
|
|
if (is_meta(instr) && ((instr->opc == OPC_META_INPUT) ||
|
|
|
|
(instr->opc == OPC_META_PHI)))
|
|
|
|
schedule(ctx, instr);
|
|
|
|
}
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
while (!(list_empty(&unscheduled_list) &&
|
|
|
|
list_empty(&prio_queue))) {
|
|
|
|
struct ir3_sched_notes notes = {0};
|
|
|
|
unsigned delay;
|
2014-07-21 20:24:30 +01:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
delay = add_eligible_instrs(ctx, ¬es, &prio_queue, &unscheduled_list);
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
if (!list_empty(&prio_queue)) {
|
|
|
|
struct ir3_instruction *instr = list_last_entry(&prio_queue,
|
|
|
|
struct ir3_instruction, node);
|
|
|
|
/* ugg, this is a bit ugly, but between the time when
|
|
|
|
* the instruction became eligible and now, a new
|
|
|
|
* conflict may have arose..
|
|
|
|
*/
|
|
|
|
if (check_conflict(ctx, ¬es, instr)) {
|
|
|
|
list_del(&instr->node);
|
|
|
|
list_addtail(&instr->node, &unscheduled_list);
|
|
|
|
continue;
|
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
schedule(ctx, instr);
|
|
|
|
} else if (delay == ~0) {
|
2015-07-02 19:59:08 +01:00
|
|
|
struct ir3_instruction *new_instr = NULL;
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
/* nothing available to schedule.. if we are blocked on
|
|
|
|
* address/predicate register conflict, then break the
|
|
|
|
* deadlock by cloning the instruction that wrote that
|
|
|
|
* reg:
|
|
|
|
*/
|
|
|
|
if (notes.addr_conflict) {
|
2015-07-02 19:59:08 +01:00
|
|
|
new_instr = split_addr(ctx);
|
2015-04-30 18:57:15 +01:00
|
|
|
} else if (notes.pred_conflict) {
|
2015-07-02 19:59:08 +01:00
|
|
|
new_instr = split_pred(ctx);
|
2015-04-30 18:57:15 +01:00
|
|
|
} else {
|
|
|
|
debug_assert(0);
|
|
|
|
ctx->error = true;
|
|
|
|
return;
|
|
|
|
}
|
2015-07-02 19:59:08 +01:00
|
|
|
|
|
|
|
if (new_instr) {
|
|
|
|
list_del(&new_instr->node);
|
|
|
|
list_addtail(&new_instr->node, &unscheduled_list);
|
2015-07-06 01:17:56 +01:00
|
|
|
/* the original instr that wrote addr/pred may have
|
|
|
|
* originated from a different block:
|
|
|
|
*/
|
|
|
|
new_instr->block = block;
|
2015-07-02 19:59:08 +01:00
|
|
|
}
|
|
|
|
|
2015-04-30 18:57:15 +01:00
|
|
|
} else {
|
|
|
|
/* and if we run out of instructions that can be scheduled,
|
|
|
|
* then it is time for nop's:
|
|
|
|
*/
|
|
|
|
debug_assert(delay <= 6);
|
|
|
|
while (delay > 0) {
|
|
|
|
ir3_NOP(block);
|
|
|
|
delay--;
|
|
|
|
}
|
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
2015-06-09 22:17:06 +01:00
|
|
|
|
|
|
|
/* And lastly, insert branch/jump instructions to take us to
|
|
|
|
* the next block. Later we'll strip back out the branches
|
|
|
|
* that simply jump to next instruction.
|
|
|
|
*/
|
|
|
|
if (block->successors[1]) {
|
|
|
|
/* if/else, conditional branches to "then" or "else": */
|
|
|
|
struct ir3_instruction *br;
|
|
|
|
unsigned delay = 6;
|
|
|
|
|
|
|
|
debug_assert(ctx->pred);
|
|
|
|
debug_assert(block->condition);
|
|
|
|
|
|
|
|
delay -= distance(ctx, ctx->pred, delay);
|
|
|
|
|
|
|
|
while (delay > 0) {
|
|
|
|
ir3_NOP(block);
|
|
|
|
delay--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* create "else" branch first (since "then" block should
|
|
|
|
* frequently/always end up being a fall-thru):
|
|
|
|
*/
|
|
|
|
br = ir3_BR(block);
|
|
|
|
br->cat0.inv = true;
|
|
|
|
br->cat0.target = block->successors[1];
|
|
|
|
|
|
|
|
/* NOTE: we have to hard code delay of 6 above, since
|
|
|
|
* we want to insert the nop's before constructing the
|
|
|
|
* branch. Throw in an assert so we notice if this
|
|
|
|
* ever breaks on future generation:
|
|
|
|
*/
|
|
|
|
debug_assert(ir3_delayslots(ctx->pred, br, 0) == 6);
|
|
|
|
|
|
|
|
br = ir3_BR(block);
|
|
|
|
br->cat0.target = block->successors[0];
|
|
|
|
|
|
|
|
} else if (block->successors[0]) {
|
|
|
|
/* otherwise unconditional jump to next block: */
|
|
|
|
struct ir3_instruction *jmp;
|
|
|
|
|
|
|
|
jmp = ir3_JUMP(block);
|
|
|
|
jmp->cat0.target = block->successors[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTE: if we kept track of the predecessors, we could do a better
|
|
|
|
* job w/ (jp) flags.. every node w/ > predecessor is a join point.
|
|
|
|
* Note that as we eliminate blocks which contain only an unconditional
|
|
|
|
* jump we probably need to propagate (jp) flag..
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
/* this is needed to ensure later RA stage succeeds: */
|
|
|
|
static void
|
|
|
|
sched_insert_parallel_copies(struct ir3_block *block)
|
|
|
|
{
|
|
|
|
list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
|
|
|
|
if (is_meta(instr) && (instr->opc == OPC_META_PHI)) {
|
|
|
|
struct ir3_register *reg;
|
|
|
|
foreach_src(reg, instr) {
|
|
|
|
struct ir3_instruction *src = reg->instr;
|
|
|
|
struct ir3_instruction *mov =
|
|
|
|
ir3_MOV(src->block, src, TYPE_U32);
|
|
|
|
mov->regs[0]->flags |= IR3_REG_PHI_SRC;
|
|
|
|
mov->regs[0]->instr = instr;
|
|
|
|
reg->instr = mov;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|
|
|
|
|
2015-05-25 15:30:54 +01:00
|
|
|
int ir3_sched(struct ir3 *ir)
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
{
|
|
|
|
struct ir3_sched_ctx ctx = {0};
|
2015-06-09 22:17:06 +01:00
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
|
|
|
sched_insert_parallel_copies(block);
|
|
|
|
}
|
|
|
|
ir3_clear_mark(ir);
|
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
|
|
|
sched_block(&ctx, block);
|
|
|
|
}
|
2014-08-29 15:51:40 +01:00
|
|
|
if (ctx.error)
|
|
|
|
return -1;
|
|
|
|
return 0;
|
freedreno/a3xx/compiler: new compiler
The new compiler generates a dependency graph of instructions, including
a few meta-instructions to handle PHI and preserve some extra
information needed for register assignment, etc.
The depth pass assigned a weight/depth to each node (based on sum of
instruction cycles of a given node and all it's dependent nodes), which
is used to schedule instructions. The scheduling takes into account the
minimum number of cycles/slots between dependent instructions, etc.
Which was something that could not be handled properly with the original
compiler (which was more of a naive TGSI translator than an actual
compiler).
The register assignment is currently split out as a standalone pass. I
expect that it will be replaced at some point, once I figure out what to
do about relative addressing (which is currently the only thing that
should cause fallback to old compiler).
There are a couple new debug options for FD_MESA_DEBUG env var:
optmsgs - enable debug prints in optimizer
optdump - dump instruction graph in .dot format, for example:
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot.png
http://people.freedesktop.org/~robclark/a3xx/frag-0000.dot
At this point, thanks to proper handling of instruction scheduling, the
new compiler fixes a lot of things that were broken before, and does not
appear to break anything that was working before[1]. So even though it
is not finished, it seems useful to merge it in it's current state.
[1] Not merged in this commit, because I'm not sure if it really belongs
in mesa tree, but the following commit implements a simple shader
emulator, which I've used to compare the output of the new compiler to
the original compiler (ie. run it on all the TGSI shaders dumped out via
ST_DEBUG=tgsi with various games/apps):
https://github.com/freedreno/mesa/commit/163b6306b1660e05ece2f00d264a8393d99b6f12
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-01-29 22:18:49 +00:00
|
|
|
}
|