2017-11-25 21:33:10 +00:00
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "radeon/radeon_video.h"
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2017-11-25 21:48:36 +00:00
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#include "radeon/radeon_vce.h"
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2017-11-25 21:33:10 +00:00
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#include "ac_llvm_util.h"
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#include "vl/vl_decoder.h"
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#include "vl/vl_video_buffer.h"
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2017-11-25 21:48:36 +00:00
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#include "util/u_video.h"
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2017-11-25 21:33:10 +00:00
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#include "compiler/nir/nir.h"
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#include <sys/utsname.h>
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static const char *si_get_vendor(struct pipe_screen *pscreen)
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{
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2017-11-25 22:04:31 +00:00
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/* Don't change this. Games such as Alien Isolation are broken if this
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* returns "Advanced Micro Devices, Inc."
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*/
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2017-11-25 21:33:10 +00:00
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return "X.Org";
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}
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static const char *si_get_device_vendor(struct pipe_screen *pscreen)
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{
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return "AMD";
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}
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static const char *si_get_marketing_name(struct radeon_winsys *ws)
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{
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if (!ws->get_chip_name)
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return NULL;
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return ws->get_chip_name(ws);
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}
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const char *si_get_family_name(const struct si_screen *sscreen)
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{
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2017-11-26 02:38:44 +00:00
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switch (sscreen->info.family) {
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2017-11-25 21:33:10 +00:00
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case CHIP_TAHITI: return "AMD TAHITI";
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case CHIP_PITCAIRN: return "AMD PITCAIRN";
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case CHIP_VERDE: return "AMD CAPE VERDE";
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case CHIP_OLAND: return "AMD OLAND";
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case CHIP_HAINAN: return "AMD HAINAN";
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case CHIP_BONAIRE: return "AMD BONAIRE";
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case CHIP_KAVERI: return "AMD KAVERI";
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case CHIP_KABINI: return "AMD KABINI";
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case CHIP_HAWAII: return "AMD HAWAII";
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case CHIP_MULLINS: return "AMD MULLINS";
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case CHIP_TONGA: return "AMD TONGA";
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case CHIP_ICELAND: return "AMD ICELAND";
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case CHIP_CARRIZO: return "AMD CARRIZO";
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case CHIP_FIJI: return "AMD FIJI";
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case CHIP_POLARIS10: return "AMD POLARIS10";
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case CHIP_POLARIS11: return "AMD POLARIS11";
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case CHIP_POLARIS12: return "AMD POLARIS12";
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case CHIP_STONEY: return "AMD STONEY";
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case CHIP_VEGA10: return "AMD VEGA10";
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case CHIP_RAVEN: return "AMD RAVEN";
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default: return "AMD unknown";
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}
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}
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static bool si_have_tgsi_compute(struct si_screen *sscreen)
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{
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/* Old kernels disallowed some register writes for SI
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* that are used for indirect dispatches. */
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2017-11-26 02:38:44 +00:00
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return (sscreen->info.chip_class >= CIK ||
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sscreen->info.drm_major == 3 ||
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(sscreen->info.drm_major == 2 &&
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sscreen->info.drm_minor >= 45));
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2017-11-25 21:33:10 +00:00
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}
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static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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{
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struct si_screen *sscreen = (struct si_screen *)pscreen;
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switch (param) {
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/* Supported features (boolean caps). */
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case PIPE_CAP_ACCELERATED:
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_POINT_SPRITE:
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_SM3:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_DRAW_INDIRECT:
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case PIPE_CAP_CLIP_HALFZ:
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case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_TGSI_TEXCOORD:
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case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_SHAREABLE_SHADERS:
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case PIPE_CAP_DEPTH_BOUNDS_TEST:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_TGSI_TXQS:
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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case PIPE_CAP_QUERY_MEMORY_INFO:
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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case PIPE_CAP_GENERATE_MIPMAP:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_CLEAR_TEXTURE:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
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case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
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case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
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case PIPE_CAP_BINDLESS_TEXTURE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
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case PIPE_CAP_QUERY_SO_OVERFLOW:
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case PIPE_CAP_MEMOBJ:
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case PIPE_CAP_LOAD_CONSTBUF:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_TGSI_CLOCK:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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case PIPE_CAP_TGSI_VOTE:
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2018-02-02 18:26:49 +00:00
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return 1;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_TGSI_BALLOT:
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return HAVE_LLVM >= 0x0500;
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case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
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2017-11-26 02:38:44 +00:00
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return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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2017-11-26 02:38:44 +00:00
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return (sscreen->info.drm_major == 2 &&
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sscreen->info.drm_minor >= 43) ||
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sscreen->info.drm_major == 3;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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/* 2D tiling on CIK is supported since DRM 2.35.0 */
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2017-11-26 02:38:44 +00:00
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return sscreen->info.chip_class < CIK ||
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(sscreen->info.drm_major == 2 &&
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sscreen->info.drm_minor >= 35) ||
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sscreen->info.drm_major == 3;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return R600_MAP_BUFFER_ALIGNMENT;
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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return 4;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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if (si_have_tgsi_compute(sscreen))
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return 450;
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return 420;
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case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
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2017-11-26 02:38:44 +00:00
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return MIN2(sscreen->info.max_alloc_size, INT_MAX);
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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/* SI doesn't support unaligned loads.
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* CIK needs DRM 2.50.0 on radeon. */
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2017-11-26 02:38:44 +00:00
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return sscreen->info.chip_class == SI ||
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(sscreen->info.drm_major == 2 &&
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sscreen->info.drm_minor < 50);
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
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/* TODO: GFX9 hangs. */
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2017-11-26 02:38:44 +00:00
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if (sscreen->info.chip_class >= GFX9)
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2017-11-25 21:33:10 +00:00
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return 0;
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/* Disable on SI due to VM faults in CP DMA. Enable once these
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* faults are mitigated in software.
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*/
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2017-11-26 02:38:44 +00:00
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if (sscreen->info.chip_class >= CIK &&
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sscreen->info.drm_major == 3 &&
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sscreen->info.drm_minor >= 13)
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2017-11-25 21:33:10 +00:00
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return RADEON_SPARSE_PAGE_SIZE;
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return 0;
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/* Unsupported features. */
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case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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case PIPE_CAP_FAKE_SW_MSAA:
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case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
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case PIPE_CAP_VERTEXID_NOBASE:
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case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
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case PIPE_CAP_MAX_WINDOW_RECTANGLES:
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case PIPE_CAP_TGSI_FS_FBFETCH:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_UMA:
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case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
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case PIPE_CAP_POST_DEPTH_COVERAGE:
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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2017-08-23 19:39:55 +01:00
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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2017-11-25 21:33:10 +00:00
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return 0;
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2017-12-20 00:31:41 +00:00
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case PIPE_CAP_FENCE_SIGNAL:
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return sscreen->info.has_syncobj;
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2017-12-31 21:58:57 +00:00
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case PIPE_CAP_CONSTBUF0_FLAGS:
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return R600_RESOURCE_FLAG_32BIT;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_NATIVE_FENCE_FD:
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2018-01-03 23:19:41 +00:00
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return sscreen->info.has_fence_to_handle;
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2017-11-25 21:33:10 +00:00
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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return si_have_tgsi_compute(sscreen);
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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return sscreen->has_draw_indirect_multi;
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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return 30;
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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2017-11-26 02:38:44 +00:00
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|
|
return sscreen->info.chip_class <= VI ?
|
2017-11-25 21:33:10 +00:00
|
|
|
PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
|
|
|
|
|
|
|
|
/* Stream output. */
|
|
|
|
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
|
|
|
|
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
|
|
|
|
return 32*4;
|
|
|
|
|
|
|
|
/* Geometry shader output. */
|
|
|
|
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
|
|
|
|
return 1024;
|
|
|
|
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
|
|
|
|
return 4095;
|
|
|
|
|
|
|
|
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
|
|
|
|
return 2048;
|
|
|
|
|
|
|
|
/* Texturing. */
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
|
|
|
|
return 15; /* 16384 */
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
|
|
|
|
/* textures support 8192, but layered rendering supports 2048 */
|
|
|
|
return 12;
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
|
|
|
|
/* textures support 8192, but layered rendering supports 2048 */
|
|
|
|
return 2048;
|
|
|
|
|
|
|
|
/* Viewports and render targets. */
|
|
|
|
case PIPE_CAP_MAX_VIEWPORTS:
|
|
|
|
return SI_MAX_VIEWPORTS;
|
|
|
|
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
|
|
|
|
case PIPE_CAP_MAX_RENDER_TARGETS:
|
|
|
|
return 8;
|
|
|
|
|
|
|
|
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
|
|
|
|
case PIPE_CAP_MIN_TEXEL_OFFSET:
|
|
|
|
return -32;
|
|
|
|
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
|
|
|
|
case PIPE_CAP_MAX_TEXEL_OFFSET:
|
|
|
|
return 31;
|
|
|
|
|
|
|
|
case PIPE_CAP_ENDIANNESS:
|
|
|
|
return PIPE_ENDIAN_LITTLE;
|
|
|
|
|
|
|
|
case PIPE_CAP_VENDOR_ID:
|
|
|
|
return ATI_VENDOR_ID;
|
|
|
|
case PIPE_CAP_DEVICE_ID:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.pci_id;
|
2017-11-25 21:33:10 +00:00
|
|
|
case PIPE_CAP_VIDEO_MEMORY:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.vram_size >> 20;
|
2017-11-25 21:33:10 +00:00
|
|
|
case PIPE_CAP_PCI_GROUP:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.pci_domain;
|
2017-11-25 21:33:10 +00:00
|
|
|
case PIPE_CAP_PCI_BUS:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.pci_bus;
|
2017-11-25 21:33:10 +00:00
|
|
|
case PIPE_CAP_PCI_DEVICE:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.pci_dev;
|
2017-11-25 21:33:10 +00:00
|
|
|
case PIPE_CAP_PCI_FUNCTION:
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->info.pci_func;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
|
|
|
|
{
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
|
|
|
|
return 8192.0f;
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
|
|
|
|
return 16.0f;
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
|
|
|
|
return 16.0f;
|
|
|
|
}
|
|
|
|
return 0.0f;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int si_get_shader_param(struct pipe_screen* pscreen,
|
|
|
|
enum pipe_shader_type shader,
|
|
|
|
enum pipe_shader_cap param)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen *)pscreen;
|
|
|
|
|
|
|
|
switch(shader)
|
|
|
|
{
|
|
|
|
case PIPE_SHADER_FRAGMENT:
|
|
|
|
case PIPE_SHADER_VERTEX:
|
|
|
|
case PIPE_SHADER_GEOMETRY:
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_COMPUTE:
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
|
|
|
|
int ir = 1 << PIPE_SHADER_IR_NATIVE;
|
|
|
|
|
|
|
|
if (si_have_tgsi_compute(sscreen))
|
|
|
|
ir |= 1 << PIPE_SHADER_IR_TGSI;
|
|
|
|
|
|
|
|
return ir;
|
|
|
|
}
|
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
|
|
|
|
uint64_t max_const_buffer_size;
|
|
|
|
pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
|
|
|
|
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
|
|
|
|
&max_const_buffer_size);
|
|
|
|
return MIN2(max_const_buffer_size, INT_MAX);
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
/* If compute shaders don't require a special value
|
|
|
|
* for this cap, we can return the same value we
|
|
|
|
* do for other shader types. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (param) {
|
|
|
|
/* Shader limits. */
|
|
|
|
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
|
|
|
|
return 16384;
|
|
|
|
case PIPE_SHADER_CAP_MAX_INPUTS:
|
|
|
|
return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
|
|
|
|
case PIPE_SHADER_CAP_MAX_OUTPUTS:
|
|
|
|
return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEMPS:
|
|
|
|
return 256; /* Max native temporaries. */
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
|
|
|
|
return 4096 * sizeof(float[4]); /* actually only memory limits this */
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
|
|
|
|
return SI_NUM_CONST_BUFFERS;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
|
|
|
|
return SI_NUM_SAMPLERS;
|
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
|
|
|
|
return SI_NUM_SHADER_BUFFERS;
|
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
|
|
|
|
return SI_NUM_IMAGES;
|
|
|
|
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
|
|
|
|
return 32;
|
|
|
|
case PIPE_SHADER_CAP_PREFERRED_IR:
|
2018-01-12 01:38:13 +00:00
|
|
|
if (sscreen->debug_flags & DBG(NIR))
|
2017-11-25 21:33:10 +00:00
|
|
|
return PIPE_SHADER_IR_NIR;
|
|
|
|
return PIPE_SHADER_IR_TGSI;
|
|
|
|
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
|
|
|
|
return 4;
|
|
|
|
|
|
|
|
/* Supported boolean features. */
|
|
|
|
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
|
|
|
|
case PIPE_SHADER_CAP_INTEGERS:
|
|
|
|
case PIPE_SHADER_CAP_INT64_ATOMICS:
|
|
|
|
case PIPE_SHADER_CAP_FP16:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
|
|
|
/* TODO: Indirect indexing of GS inputs is unimplemented. */
|
|
|
|
return shader != PIPE_SHADER_GEOMETRY &&
|
|
|
|
(sscreen->llvm_has_working_vgpr_indexing ||
|
|
|
|
/* TCS and TES load inputs directly from LDS or
|
|
|
|
* offchip memory, so indirect indexing is trivial. */
|
|
|
|
shader == PIPE_SHADER_TESS_CTRL ||
|
|
|
|
shader == PIPE_SHADER_TESS_EVAL);
|
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
|
|
|
return sscreen->llvm_has_working_vgpr_indexing ||
|
|
|
|
/* TCS stores outputs directly to memory. */
|
|
|
|
shader == PIPE_SHADER_TESS_CTRL;
|
|
|
|
|
|
|
|
/* Unsupported boolean features. */
|
|
|
|
case PIPE_SHADER_CAP_SUBROUTINES:
|
|
|
|
case PIPE_SHADER_CAP_SUPPORTED_IRS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct nir_shader_compiler_options nir_options = {
|
|
|
|
.vertex_id_zero_based = true,
|
|
|
|
.lower_scmp = true,
|
|
|
|
.lower_flrp32 = true,
|
2018-01-12 00:12:09 +00:00
|
|
|
.lower_flrp64 = true,
|
2017-11-25 21:33:10 +00:00
|
|
|
.lower_fsat = true,
|
|
|
|
.lower_fdiv = true,
|
|
|
|
.lower_sub = true,
|
|
|
|
.lower_ffma = true,
|
|
|
|
.lower_pack_snorm_2x16 = true,
|
|
|
|
.lower_pack_snorm_4x8 = true,
|
|
|
|
.lower_pack_unorm_2x16 = true,
|
|
|
|
.lower_pack_unorm_4x8 = true,
|
|
|
|
.lower_unpack_snorm_2x16 = true,
|
|
|
|
.lower_unpack_snorm_4x8 = true,
|
|
|
|
.lower_unpack_unorm_2x16 = true,
|
|
|
|
.lower_unpack_unorm_4x8 = true,
|
|
|
|
.lower_extract_byte = true,
|
|
|
|
.lower_extract_word = true,
|
|
|
|
.max_unroll_iterations = 32,
|
|
|
|
.native_integers = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const void *
|
|
|
|
si_get_compiler_options(struct pipe_screen *screen,
|
|
|
|
enum pipe_shader_ir ir,
|
|
|
|
enum pipe_shader_type shader)
|
|
|
|
{
|
|
|
|
assert(ir == PIPE_SHADER_IR_NIR);
|
|
|
|
return &nir_options;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
|
|
|
|
{
|
|
|
|
ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen *)pscreen;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const char* si_get_name(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen*)pscreen;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->renderer_string;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int si_get_video_param_no_decode(struct pipe_screen *screen,
|
|
|
|
enum pipe_video_profile profile,
|
|
|
|
enum pipe_video_entrypoint entrypoint,
|
|
|
|
enum pipe_video_cap param)
|
|
|
|
{
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTED:
|
|
|
|
return vl_profile_supported(screen, profile, entrypoint);
|
|
|
|
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
|
|
|
|
return 1;
|
|
|
|
case PIPE_VIDEO_CAP_MAX_WIDTH:
|
|
|
|
case PIPE_VIDEO_CAP_MAX_HEIGHT:
|
|
|
|
return vl_video_buffer_max_size(screen);
|
|
|
|
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
|
|
|
|
return PIPE_FORMAT_NV12;
|
|
|
|
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
|
|
|
|
return false;
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
|
|
|
|
return false;
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
|
|
|
|
return true;
|
|
|
|
case PIPE_VIDEO_CAP_MAX_LEVEL:
|
|
|
|
return vl_level_supported(screen, profile);
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-25 21:48:36 +00:00
|
|
|
static int si_get_video_param(struct pipe_screen *screen,
|
|
|
|
enum pipe_video_profile profile,
|
|
|
|
enum pipe_video_entrypoint entrypoint,
|
|
|
|
enum pipe_video_cap param)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen *)screen;
|
|
|
|
enum pipe_video_format codec = u_reduce_video_profile(profile);
|
|
|
|
|
|
|
|
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTED:
|
2018-01-25 20:06:35 +00:00
|
|
|
return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
|
2017-11-26 02:38:44 +00:00
|
|
|
(si_vce_is_fw_version_supported(sscreen) ||
|
2018-01-25 20:06:35 +00:00
|
|
|
sscreen->info.family == CHIP_RAVEN)) ||
|
|
|
|
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
|
2017-11-26 02:38:44 +00:00
|
|
|
sscreen->info.family == CHIP_RAVEN);
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
|
|
|
|
return 1;
|
|
|
|
case PIPE_VIDEO_CAP_MAX_WIDTH:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_CAP_MAX_HEIGHT:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
|
|
|
|
return PIPE_FORMAT_NV12;
|
|
|
|
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
|
|
|
|
return false;
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
|
|
|
|
return false;
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
|
|
|
|
return true;
|
|
|
|
case PIPE_VIDEO_CAP_STACKED_FRAMES:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
|
2017-11-25 21:48:36 +00:00
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTED:
|
|
|
|
switch (codec) {
|
|
|
|
case PIPE_VIDEO_FORMAT_MPEG12:
|
|
|
|
return profile != PIPE_VIDEO_PROFILE_MPEG1;
|
|
|
|
case PIPE_VIDEO_FORMAT_MPEG4:
|
|
|
|
return 1;
|
|
|
|
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
|
2017-11-26 02:38:44 +00:00
|
|
|
if ((sscreen->info.family == CHIP_POLARIS10 ||
|
|
|
|
sscreen->info.family == CHIP_POLARIS11) &&
|
|
|
|
sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
|
2017-11-25 21:48:36 +00:00
|
|
|
RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
case PIPE_VIDEO_FORMAT_VC1:
|
|
|
|
return true;
|
|
|
|
case PIPE_VIDEO_FORMAT_HEVC:
|
|
|
|
/* Carrizo only supports HEVC Main */
|
2017-11-26 02:38:44 +00:00
|
|
|
if (sscreen->info.family >= CHIP_STONEY)
|
2017-11-25 21:48:36 +00:00
|
|
|
return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
|
|
|
|
profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
|
2017-11-26 02:38:44 +00:00
|
|
|
else if (sscreen->info.family >= CHIP_CARRIZO)
|
2017-11-25 21:48:36 +00:00
|
|
|
return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
|
|
|
|
return false;
|
|
|
|
case PIPE_VIDEO_FORMAT_JPEG:
|
2017-11-26 02:38:44 +00:00
|
|
|
if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
|
2017-11-25 21:48:36 +00:00
|
|
|
return false;
|
2017-11-26 02:38:44 +00:00
|
|
|
if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
|
2017-11-25 21:48:36 +00:00
|
|
|
RVID_ERR("No MJPEG support for the kernel version\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
|
|
|
|
return 1;
|
|
|
|
case PIPE_VIDEO_CAP_MAX_WIDTH:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_CAP_MAX_HEIGHT:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
|
|
|
|
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
|
|
|
|
return PIPE_FORMAT_P016;
|
|
|
|
else
|
|
|
|
return PIPE_FORMAT_NV12;
|
|
|
|
|
|
|
|
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
|
|
|
|
enum pipe_video_format format = u_reduce_video_profile(profile);
|
|
|
|
|
|
|
|
if (format == PIPE_VIDEO_FORMAT_HEVC)
|
|
|
|
return false; //The firmware doesn't support interlaced HEVC.
|
|
|
|
else if (format == PIPE_VIDEO_FORMAT_JPEG)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
|
|
|
|
return true;
|
|
|
|
case PIPE_VIDEO_CAP_MAX_LEVEL:
|
|
|
|
switch (profile) {
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG1:
|
|
|
|
return 0;
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
|
|
|
|
return 3;
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
|
|
|
|
return 3;
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
|
|
|
|
return 5;
|
|
|
|
case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
|
|
|
|
return 1;
|
|
|
|
case PIPE_VIDEO_PROFILE_VC1_MAIN:
|
|
|
|
return 2;
|
|
|
|
case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
|
|
|
|
return 4;
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
|
|
|
|
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
|
2017-11-26 02:38:44 +00:00
|
|
|
return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
|
2017-11-25 21:48:36 +00:00
|
|
|
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
|
|
|
|
case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
|
|
|
|
return 186;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static boolean si_vid_is_format_supported(struct pipe_screen *screen,
|
|
|
|
enum pipe_format format,
|
|
|
|
enum pipe_video_profile profile,
|
|
|
|
enum pipe_video_entrypoint entrypoint)
|
|
|
|
{
|
|
|
|
/* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
|
|
|
|
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
|
|
|
|
return (format == PIPE_FORMAT_NV12) ||
|
|
|
|
(format == PIPE_FORMAT_P016);
|
|
|
|
|
|
|
|
/* we can only handle this one with UVD */
|
|
|
|
if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
|
|
|
|
return format == PIPE_FORMAT_NV12;
|
|
|
|
|
|
|
|
return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
|
|
|
|
}
|
|
|
|
|
2017-11-25 21:33:10 +00:00
|
|
|
static unsigned get_max_threads_per_block(struct si_screen *screen,
|
|
|
|
enum pipe_shader_ir ir_type)
|
|
|
|
{
|
2018-02-01 23:09:47 +00:00
|
|
|
if (ir_type == PIPE_SHADER_IR_NATIVE)
|
2017-11-25 21:33:10 +00:00
|
|
|
return 256;
|
|
|
|
|
|
|
|
/* Only 16 waves per thread-group on gfx9. */
|
2017-11-26 02:38:44 +00:00
|
|
|
if (screen->info.chip_class >= GFX9)
|
2017-11-25 21:33:10 +00:00
|
|
|
return 1024;
|
|
|
|
|
|
|
|
/* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
|
|
|
|
* round number.
|
|
|
|
*/
|
|
|
|
return 2048;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int si_get_compute_param(struct pipe_screen *screen,
|
|
|
|
enum pipe_shader_ir ir_type,
|
|
|
|
enum pipe_compute_cap param,
|
|
|
|
void *ret)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen *)screen;
|
|
|
|
|
|
|
|
//TODO: select these params by asic
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_COMPUTE_CAP_IR_TARGET: {
|
2018-02-02 18:26:49 +00:00
|
|
|
const char *gpu, *triple;
|
2017-11-25 21:33:10 +00:00
|
|
|
|
2018-02-02 18:26:49 +00:00
|
|
|
triple = "amdgcn-mesa-mesa3d";
|
2017-11-26 02:38:44 +00:00
|
|
|
gpu = ac_get_llvm_processor_name(sscreen->info.family);
|
2017-11-25 21:33:10 +00:00
|
|
|
if (ret) {
|
|
|
|
sprintf(ret, "%s-%s", gpu, triple);
|
|
|
|
}
|
|
|
|
/* +2 for dash and terminating NIL byte */
|
|
|
|
return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
|
|
|
|
}
|
|
|
|
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *grid_dimension = ret;
|
|
|
|
grid_dimension[0] = 3;
|
|
|
|
}
|
|
|
|
return 1 * sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *grid_size = ret;
|
|
|
|
grid_size[0] = 65535;
|
|
|
|
grid_size[1] = 65535;
|
|
|
|
grid_size[2] = 65535;
|
|
|
|
}
|
|
|
|
return 3 * sizeof(uint64_t) ;
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *block_size = ret;
|
|
|
|
unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
|
|
|
|
block_size[0] = threads_per_block;
|
|
|
|
block_size[1] = threads_per_block;
|
|
|
|
block_size[2] = threads_per_block;
|
|
|
|
}
|
|
|
|
return 3 * sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_threads_per_block = ret;
|
|
|
|
*max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
|
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
|
|
|
|
if (ret) {
|
|
|
|
uint32_t *address_bits = ret;
|
|
|
|
address_bits[0] = 64;
|
|
|
|
}
|
|
|
|
return 1 * sizeof(uint32_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_global_size = ret;
|
|
|
|
uint64_t max_mem_alloc_size;
|
|
|
|
|
|
|
|
si_get_compute_param(screen, ir_type,
|
|
|
|
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
|
|
|
|
&max_mem_alloc_size);
|
|
|
|
|
|
|
|
/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
|
|
|
|
* 1/4 of the MAX_GLOBAL_SIZE. Since the
|
|
|
|
* MAX_MEM_ALLOC_SIZE is fixed for older kernels,
|
|
|
|
* make sure we never report more than
|
|
|
|
* 4 * MAX_MEM_ALLOC_SIZE.
|
|
|
|
*/
|
|
|
|
*max_global_size = MIN2(4 * max_mem_alloc_size,
|
2017-11-26 02:38:44 +00:00
|
|
|
MAX2(sscreen->info.gart_size,
|
|
|
|
sscreen->info.vram_size));
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_local_size = ret;
|
|
|
|
/* Value reported by the closed source driver. */
|
|
|
|
*max_local_size = 32768;
|
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_input_size = ret;
|
|
|
|
/* Value reported by the closed source driver. */
|
|
|
|
*max_input_size = 1024;
|
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_mem_alloc_size = ret;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
*max_mem_alloc_size = sscreen->info.max_alloc_size;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
|
|
|
|
if (ret) {
|
|
|
|
uint32_t *max_clock_frequency = ret;
|
2017-11-26 02:38:44 +00:00
|
|
|
*max_clock_frequency = sscreen->info.max_shader_clock;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return sizeof(uint32_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
|
|
|
|
if (ret) {
|
|
|
|
uint32_t *max_compute_units = ret;
|
2017-11-26 02:38:44 +00:00
|
|
|
*max_compute_units = sscreen->info.num_good_compute_units;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return sizeof(uint32_t);
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
|
|
|
|
if (ret) {
|
|
|
|
uint32_t *images_supported = ret;
|
|
|
|
*images_supported = 0;
|
|
|
|
}
|
|
|
|
return sizeof(uint32_t);
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
|
|
|
|
break; /* unused */
|
|
|
|
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
|
|
|
|
if (ret) {
|
|
|
|
uint32_t *subgroup_size = ret;
|
|
|
|
*subgroup_size = 64;
|
|
|
|
}
|
|
|
|
return sizeof(uint32_t);
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
|
|
|
|
if (ret) {
|
|
|
|
uint64_t *max_variable_threads_per_block = ret;
|
2018-02-01 23:09:47 +00:00
|
|
|
if (ir_type == PIPE_SHADER_IR_NATIVE)
|
2017-11-25 21:33:10 +00:00
|
|
|
*max_variable_threads_per_block = 0;
|
2018-02-01 23:09:47 +00:00
|
|
|
else
|
|
|
|
*max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
return sizeof(uint64_t);
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t si_get_timestamp(struct pipe_screen *screen)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen*)screen;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
|
|
|
|
sscreen->info.clock_crystal_freq;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void si_query_memory_info(struct pipe_screen *screen,
|
|
|
|
struct pipe_memory_info *info)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen*)screen;
|
2017-11-26 02:38:44 +00:00
|
|
|
struct radeon_winsys *ws = sscreen->ws;
|
2017-11-25 21:33:10 +00:00
|
|
|
unsigned vram_usage, gtt_usage;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
info->total_device_memory = sscreen->info.vram_size / 1024;
|
|
|
|
info->total_staging_memory = sscreen->info.gart_size / 1024;
|
2017-11-25 21:33:10 +00:00
|
|
|
|
|
|
|
/* The real TTM memory usage is somewhat random, because:
|
|
|
|
*
|
|
|
|
* 1) TTM delays freeing memory, because it can only free it after
|
|
|
|
* fences expire.
|
|
|
|
*
|
|
|
|
* 2) The memory usage can be really low if big VRAM evictions are
|
|
|
|
* taking place, but the real usage is well above the size of VRAM.
|
|
|
|
*
|
|
|
|
* Instead, return statistics of this process.
|
|
|
|
*/
|
|
|
|
vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
|
|
|
|
gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
|
|
|
|
|
|
|
|
info->avail_device_memory =
|
|
|
|
vram_usage <= info->total_device_memory ?
|
|
|
|
info->total_device_memory - vram_usage : 0;
|
|
|
|
info->avail_staging_memory =
|
|
|
|
gtt_usage <= info->total_staging_memory ?
|
|
|
|
info->total_staging_memory - gtt_usage : 0;
|
|
|
|
|
|
|
|
info->device_memory_evicted =
|
|
|
|
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
|
2017-11-25 21:33:10 +00:00
|
|
|
info->nr_device_memory_evictions =
|
|
|
|
ws->query_value(ws, RADEON_NUM_EVICTIONS);
|
|
|
|
else
|
|
|
|
/* Just return the number of evicted 64KB pages. */
|
|
|
|
info->nr_device_memory_evictions = info->device_memory_evicted / 64;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
struct si_screen *sscreen = (struct si_screen*)pscreen;
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
return sscreen->disk_shader_cache;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void si_init_renderer_string(struct si_screen *sscreen)
|
|
|
|
{
|
2017-11-26 02:38:44 +00:00
|
|
|
struct radeon_winsys *ws = sscreen->ws;
|
2017-11-25 21:33:10 +00:00
|
|
|
char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
|
|
|
|
struct utsname uname_data;
|
|
|
|
|
|
|
|
const char *chip_name = si_get_marketing_name(ws);
|
|
|
|
|
|
|
|
if (chip_name)
|
|
|
|
snprintf(family_name, sizeof(family_name), "%s / ",
|
|
|
|
si_get_family_name(sscreen) + 4);
|
|
|
|
else
|
|
|
|
chip_name = si_get_family_name(sscreen);
|
|
|
|
|
|
|
|
if (uname(&uname_data) == 0)
|
|
|
|
snprintf(kernel_version, sizeof(kernel_version),
|
|
|
|
" / %s", uname_data.release);
|
|
|
|
|
|
|
|
if (HAVE_LLVM > 0) {
|
|
|
|
snprintf(llvm_string, sizeof(llvm_string),
|
|
|
|
", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
|
|
|
|
HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
|
|
|
|
}
|
|
|
|
|
2017-11-26 02:38:44 +00:00
|
|
|
snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
|
2017-11-25 21:33:10 +00:00
|
|
|
"%s (%sDRM %i.%i.%i%s%s)",
|
2017-11-26 02:38:44 +00:00
|
|
|
chip_name, family_name, sscreen->info.drm_major,
|
|
|
|
sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
|
2017-11-25 21:33:10 +00:00
|
|
|
kernel_version, llvm_string);
|
|
|
|
}
|
|
|
|
|
|
|
|
void si_init_screen_get_functions(struct si_screen *sscreen)
|
|
|
|
{
|
2017-11-26 02:38:44 +00:00
|
|
|
sscreen->b.get_name = si_get_name;
|
|
|
|
sscreen->b.get_vendor = si_get_vendor;
|
|
|
|
sscreen->b.get_device_vendor = si_get_device_vendor;
|
|
|
|
sscreen->b.get_param = si_get_param;
|
|
|
|
sscreen->b.get_paramf = si_get_paramf;
|
|
|
|
sscreen->b.get_compute_param = si_get_compute_param;
|
|
|
|
sscreen->b.get_timestamp = si_get_timestamp;
|
|
|
|
sscreen->b.get_shader_param = si_get_shader_param;
|
|
|
|
sscreen->b.get_compiler_options = si_get_compiler_options;
|
|
|
|
sscreen->b.get_device_uuid = si_get_device_uuid;
|
|
|
|
sscreen->b.get_driver_uuid = si_get_driver_uuid;
|
|
|
|
sscreen->b.query_memory_info = si_query_memory_info;
|
|
|
|
sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
|
|
|
|
|
|
|
|
if (sscreen->info.has_hw_decode) {
|
|
|
|
sscreen->b.get_video_param = si_get_video_param;
|
|
|
|
sscreen->b.is_video_format_supported = si_vid_is_format_supported;
|
2017-11-25 21:33:10 +00:00
|
|
|
} else {
|
2017-11-26 02:38:44 +00:00
|
|
|
sscreen->b.get_video_param = si_get_video_param_no_decode;
|
|
|
|
sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
|
2017-11-25 21:33:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
si_init_renderer_string(sscreen);
|
|
|
|
}
|