2012-07-17 13:09:03 +01:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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2018-04-01 21:49:48 +01:00
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* All Rights Reserved.
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2012-07-17 13:09:03 +01:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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2014-01-04 17:44:33 +00:00
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#include "si_pipe.h"
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2020-05-24 13:34:23 +01:00
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#include "si_build_pm4.h"
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2012-07-17 13:09:03 +01:00
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#include "sid.h"
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2020-03-27 18:32:38 +00:00
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#include "util/u_memory.h"
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2012-07-17 13:09:03 +01:00
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2020-06-16 03:39:00 +01:00
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static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
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2012-08-02 13:30:06 +01:00
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{
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2020-06-16 03:39:00 +01:00
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assert(state->ndw < SI_PM4_MAX_DW);
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2020-03-27 18:32:38 +00:00
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state->last_opcode = opcode;
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state->last_pm4 = state->ndw++;
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2012-08-02 13:30:06 +01:00
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}
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void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
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{
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2020-06-16 03:39:00 +01:00
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assert(state->ndw < SI_PM4_MAX_DW);
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2020-03-27 18:32:38 +00:00
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state->pm4[state->ndw++] = dw;
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2020-11-23 04:19:44 +00:00
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state->last_opcode = -1;
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2012-08-02 13:30:06 +01:00
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}
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2020-06-16 03:39:00 +01:00
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static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
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2012-08-02 13:30:06 +01:00
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{
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2020-03-27 18:32:38 +00:00
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unsigned count;
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count = state->ndw - state->last_pm4 - 2;
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state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
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2012-08-02 13:30:06 +01:00
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}
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2012-07-17 13:09:03 +01:00
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void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
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{
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2020-03-27 18:32:38 +00:00
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unsigned opcode;
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2012-07-17 13:09:03 +01:00
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2020-05-24 13:34:23 +01:00
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SI_CHECK_SHADOWED_REGS(reg, 1);
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2020-03-27 18:32:38 +00:00
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if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
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opcode = PKT3_SET_CONFIG_REG;
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reg -= SI_CONFIG_REG_OFFSET;
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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} else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
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opcode = PKT3_SET_SH_REG;
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reg -= SI_SH_REG_OFFSET;
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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} else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
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opcode = PKT3_SET_CONTEXT_REG;
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reg -= SI_CONTEXT_REG_OFFSET;
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2012-09-28 17:09:16 +01:00
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2020-03-27 18:32:38 +00:00
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} else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
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opcode = PKT3_SET_UCONFIG_REG;
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reg -= CIK_UCONFIG_REG_OFFSET;
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2012-11-08 23:59:46 +00:00
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2020-03-27 18:32:38 +00:00
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} else {
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PRINT_ERR("Invalid register offset %08x!\n", reg);
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return;
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}
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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reg >>= 2;
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2012-07-17 13:09:03 +01:00
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2020-11-23 04:19:44 +00:00
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assert(state->ndw + 2 <= SI_PM4_MAX_DW);
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2020-03-27 18:32:38 +00:00
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if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
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si_pm4_cmd_begin(state, opcode);
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2020-11-23 04:19:44 +00:00
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state->pm4[state->ndw++] = reg;
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2020-03-27 18:32:38 +00:00
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}
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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state->last_reg = reg;
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2020-11-23 04:19:44 +00:00
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state->pm4[state->ndw++] = val;
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2020-03-27 18:32:38 +00:00
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si_pm4_cmd_end(state, false);
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2012-07-17 13:09:03 +01:00
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}
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2016-06-11 20:07:14 +01:00
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void si_pm4_clear_state(struct si_pm4_state *state)
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2015-01-27 14:52:37 +00:00
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{
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2020-03-27 18:32:38 +00:00
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state->ndw = 0;
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2016-06-11 20:07:14 +01:00
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}
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2020-03-27 18:32:38 +00:00
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void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
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2012-07-17 13:09:03 +01:00
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{
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2020-03-27 18:32:38 +00:00
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if (!state)
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return;
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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if (idx != ~0 && sctx->emitted.array[idx] == state) {
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sctx->emitted.array[idx] = NULL;
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}
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2012-07-17 13:09:03 +01:00
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2020-03-27 18:32:38 +00:00
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si_pm4_clear_state(state);
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FREE(state);
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2012-07-17 13:09:03 +01:00
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}
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2014-01-11 15:00:50 +00:00
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void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
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2012-07-17 13:09:03 +01:00
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{
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2020-11-29 09:09:02 +00:00
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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2020-03-27 18:32:38 +00:00
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2020-06-16 03:21:50 +01:00
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if (state->shader) {
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2020-11-29 09:09:02 +00:00
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, state->shader->bo,
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2020-06-16 03:21:50 +01:00
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RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
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2020-03-27 18:32:38 +00:00
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}
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2021-01-09 20:14:22 +00:00
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radeon_begin(cs);
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2020-05-24 13:34:30 +01:00
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radeon_emit_array(cs, state->pm4, state->ndw);
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2021-01-09 20:14:22 +00:00
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radeon_end();
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2020-03-27 18:32:38 +00:00
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if (state->atom.emit)
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state->atom.emit(sctx);
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2012-08-02 15:15:40 +01:00
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}
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2020-03-10 22:46:17 +00:00
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void si_pm4_reset_emitted(struct si_context *sctx, bool first_cs)
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2012-07-17 13:09:03 +01:00
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{
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2020-03-10 22:46:17 +00:00
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if (!first_cs && sctx->shadowed_regs) {
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/* Only dirty states that contain buffers, so that they are
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* added to the buffer list on the next draw call.
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*/
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for (unsigned i = 0; i < SI_NUM_STATES; i++) {
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struct si_pm4_state *state = sctx->emitted.array[i];
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if (state && state->shader) {
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sctx->emitted.array[i] = NULL;
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sctx->dirty_states |= 1 << i;
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}
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}
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return;
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}
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2020-03-27 18:32:38 +00:00
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memset(&sctx->emitted, 0, sizeof(sctx->emitted));
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2021-01-09 13:10:13 +00:00
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for (unsigned i = 0; i < SI_NUM_STATES; i++) {
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if (sctx->queued.array[i])
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sctx->dirty_states |= BITFIELD_BIT(i);
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}
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2012-07-17 13:09:03 +01:00
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}
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