2010-05-08 21:09:24 +01:00
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/*
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* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse
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* Corbin Simpson
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*/
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2010-08-22 19:22:00 +01:00
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#include <errno.h>
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2010-05-08 21:09:24 +01:00
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#include <pipe/p_screen.h>
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#include <util/u_format.h>
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#include <util/u_math.h>
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#include <util/u_inlines.h>
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#include <util/u_memory.h>
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2010-06-24 01:10:18 +01:00
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#include "state_tracker/drm_driver.h"
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2010-05-08 21:09:24 +01:00
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#include "r600_screen.h"
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2010-07-28 01:15:17 +01:00
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#include "r600_context.h"
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2010-07-28 17:18:19 +01:00
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#include "r600_resource.h"
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2010-08-22 19:22:00 +01:00
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#include "r600_state_inlines.h"
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2010-08-12 07:06:40 +01:00
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#include "r600d.h"
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2010-05-08 21:09:24 +01:00
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2010-05-10 02:27:58 +01:00
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extern struct u_resource_vtbl r600_texture_vtbl;
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2010-08-22 03:49:22 +01:00
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/* Copy from a tiled texture to a detiled one. */
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static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
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{
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struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
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struct pipe_resource *texture = transfer->resource;
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struct pipe_subresource subdst;
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subdst.face = 0;
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subdst.level = 0;
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ctx->resource_copy_region(ctx, rtransfer->linear_texture,
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subdst, 0, 0, 0, texture, transfer->sr,
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transfer->box.x, transfer->box.y, transfer->box.z,
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transfer->box.width, transfer->box.height);
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}
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2010-07-28 17:18:19 +01:00
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static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
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unsigned level, unsigned zslice,
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unsigned face)
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2010-05-08 21:09:24 +01:00
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{
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unsigned long offset = rtex->offset[level];
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2010-07-28 17:18:19 +01:00
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switch (rtex->resource.base.b.target) {
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2010-05-08 21:09:24 +01:00
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case PIPE_TEXTURE_3D:
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assert(face == 0);
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return offset + zslice * rtex->layer_size[level];
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case PIPE_TEXTURE_CUBE:
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assert(zslice == 0);
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return offset + face * rtex->layer_size[level];
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default:
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assert(zslice == 0 && face == 0);
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return offset;
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}
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}
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2010-07-28 17:18:19 +01:00
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static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
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2010-05-08 21:09:24 +01:00
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{
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2010-07-28 17:18:19 +01:00
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struct pipe_resource *ptex = &rtex->resource.base.b;
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2010-07-29 19:51:06 +01:00
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unsigned long w, h, pitch, size, layer_size, i, offset;
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2010-05-08 21:09:24 +01:00
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2010-07-29 19:51:06 +01:00
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rtex->bpt = util_format_get_blocksize(ptex->format);
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2010-05-08 21:09:24 +01:00
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for (i = 0, offset = 0; i <= ptex->last_level; i++) {
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w = u_minify(ptex->width0, i);
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h = u_minify(ptex->height0, i);
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2010-08-18 01:50:19 +01:00
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h = util_next_power_of_two(h);
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2010-07-29 19:51:06 +01:00
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pitch = util_format_get_stride(ptex->format, align(w, 64));
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2010-08-18 02:49:51 +01:00
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pitch = align(pitch, 256);
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2010-07-29 19:51:06 +01:00
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layer_size = pitch * h;
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2010-05-08 21:09:24 +01:00
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if (ptex->target == PIPE_TEXTURE_CUBE)
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size = layer_size * 6;
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else
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size = layer_size * u_minify(ptex->depth0, i);
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rtex->offset[i] = offset;
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rtex->layer_size[i] = layer_size;
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2010-07-29 19:51:06 +01:00
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rtex->pitch[i] = pitch;
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2010-08-22 19:22:00 +01:00
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rtex->width[i] = w;
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rtex->height[i] = h;
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2010-07-29 19:51:06 +01:00
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offset += size;
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2010-05-08 21:09:24 +01:00
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}
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rtex->size = offset;
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}
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2010-05-10 02:27:58 +01:00
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struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
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2010-07-28 17:18:19 +01:00
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const struct pipe_resource *templ)
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2010-05-08 21:09:24 +01:00
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{
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2010-07-28 17:18:19 +01:00
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struct r600_resource_texture *rtex;
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struct r600_resource *resource;
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2010-05-08 21:09:24 +01:00
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struct r600_screen *rscreen = r600_screen(screen);
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2010-07-28 17:18:19 +01:00
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rtex = CALLOC_STRUCT(r600_resource_texture);
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2010-05-08 21:09:24 +01:00
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if (!rtex) {
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return NULL;
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}
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2010-07-28 17:18:19 +01:00
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resource = &rtex->resource;
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resource->base.b = *templ;
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resource->base.vtbl = &r600_texture_vtbl;
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pipe_reference_init(&resource->base.b.reference, 1);
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resource->base.b.screen = screen;
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2010-05-08 21:09:24 +01:00
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r600_setup_miptree(rscreen, rtex);
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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/* FIXME alignment 4096 enought ? too much ? */
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resource->domain = r600_domain_from_usage(resource->base.b.bind);
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resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
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if (resource->bo == NULL) {
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2010-05-08 21:09:24 +01:00
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FREE(rtex);
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return NULL;
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}
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2010-07-28 17:18:19 +01:00
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return &resource->base.b;
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2010-05-08 21:09:24 +01:00
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}
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2010-09-01 18:04:42 +01:00
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static void r600_texture_destroy_state(struct pipe_resource *ptexture)
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{
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struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
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for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
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2010-08-30 22:56:59 +01:00
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radeon_state_fini(&rtexture->scissor[i]);
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radeon_state_fini(&rtexture->db[i]);
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2010-09-01 18:04:42 +01:00
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for (int j = 0; j < 8; j++) {
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2010-08-30 22:56:59 +01:00
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radeon_state_fini(&rtexture->cb[j][i]);
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2010-09-01 18:04:42 +01:00
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}
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}
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}
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2010-05-10 02:27:58 +01:00
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static void r600_texture_destroy(struct pipe_screen *screen,
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struct pipe_resource *ptex)
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2010-05-08 21:09:24 +01:00
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{
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2010-07-28 17:18:19 +01:00
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
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struct r600_resource *resource = &rtex->resource;
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struct r600_screen *rscreen = r600_screen(screen);
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2010-05-08 21:09:24 +01:00
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2010-07-28 17:18:19 +01:00
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if (resource->bo) {
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radeon_bo_decref(rscreen->rw, resource->bo);
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}
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2010-08-22 19:22:00 +01:00
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if (rtex->uncompressed) {
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radeon_bo_decref(rscreen->rw, rtex->uncompressed);
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}
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2010-09-01 18:04:42 +01:00
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r600_texture_destroy_state(ptex);
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2010-05-08 21:09:24 +01:00
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FREE(rtex);
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}
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static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
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2010-05-10 02:27:58 +01:00
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struct pipe_resource *texture,
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2010-05-08 21:09:24 +01:00
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unsigned face, unsigned level,
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unsigned zslice, unsigned flags)
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{
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2010-07-28 17:18:19 +01:00
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
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2010-05-08 21:09:24 +01:00
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struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
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unsigned long offset;
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if (surface == NULL)
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return NULL;
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offset = r600_texture_get_offset(rtex, level, zslice, face);
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pipe_reference_init(&surface->reference, 1);
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2010-05-10 02:27:58 +01:00
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pipe_resource_reference(&surface->texture, texture);
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2010-05-08 21:09:24 +01:00
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surface->format = texture->format;
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surface->width = u_minify(texture->width0, level);
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surface->height = u_minify(texture->height0, level);
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surface->offset = offset;
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surface->usage = flags;
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surface->zslice = zslice;
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surface->texture = texture;
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surface->face = face;
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surface->level = level;
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return surface;
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}
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static void r600_tex_surface_destroy(struct pipe_surface *surface)
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{
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2010-05-10 02:27:58 +01:00
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pipe_resource_reference(&surface->texture, NULL);
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2010-05-08 21:09:24 +01:00
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FREE(surface);
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}
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2010-05-10 02:27:58 +01:00
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struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
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2010-07-28 17:18:19 +01:00
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const struct pipe_resource *templ,
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2010-05-10 02:27:58 +01:00
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struct winsys_handle *whandle)
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2010-05-08 21:09:24 +01:00
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{
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2010-07-28 17:18:19 +01:00
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struct radeon *rw = (struct radeon*)screen->winsys;
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struct r600_resource_texture *rtex;
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struct r600_resource *resource;
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struct radeon_bo *bo = NULL;
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2010-05-08 21:09:24 +01:00
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2010-07-28 17:18:19 +01:00
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bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
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if (bo == NULL) {
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2010-05-10 02:27:58 +01:00
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return NULL;
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}
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2010-05-08 21:09:24 +01:00
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/* Support only 2D textures without mipmaps */
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2010-08-18 16:28:08 +01:00
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if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
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templ->depth0 != 1 || templ->last_level != 0)
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2010-05-08 21:09:24 +01:00
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return NULL;
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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rtex = CALLOC_STRUCT(r600_resource_texture);
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2010-05-08 21:09:24 +01:00
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if (rtex == NULL)
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return NULL;
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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resource = &rtex->resource;
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resource->base.b = *templ;
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resource->base.vtbl = &r600_texture_vtbl;
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pipe_reference_init(&resource->base.b.reference, 1);
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resource->base.b.screen = screen;
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resource->bo = bo;
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2010-09-01 18:04:42 +01:00
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rtex->depth = 0;
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2010-07-29 19:51:06 +01:00
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rtex->pitch_override = whandle->stride;
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rtex->bpt = util_format_get_blocksize(templ->format);
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rtex->pitch[0] = whandle->stride;
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2010-09-01 18:04:42 +01:00
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rtex->width[0] = templ->width0;
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rtex->height[0] = templ->height0;
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2010-05-08 21:09:24 +01:00
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rtex->offset[0] = 0;
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2010-07-29 19:51:06 +01:00
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rtex->size = align(rtex->pitch[0] * templ->height0, 64);
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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return &resource->base.b;
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2010-05-08 21:09:24 +01:00
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}
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2010-07-28 17:18:19 +01:00
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static unsigned int r600_texture_is_referenced(struct pipe_context *context,
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struct pipe_resource *texture,
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unsigned face, unsigned level)
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2010-05-08 21:09:24 +01:00
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{
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2010-07-28 17:18:19 +01:00
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/* FIXME */
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return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
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}
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
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struct pipe_resource *texture,
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struct pipe_subresource sr,
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unsigned usage,
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const struct pipe_box *box)
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{
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
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2010-08-22 03:49:22 +01:00
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struct pipe_resource resource;
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2010-07-28 17:18:19 +01:00
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struct r600_transfer *trans;
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2010-05-10 02:27:58 +01:00
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2010-07-28 17:18:19 +01:00
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trans = CALLOC_STRUCT(r600_transfer);
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if (trans == NULL)
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return NULL;
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pipe_resource_reference(&trans->transfer.resource, texture);
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trans->transfer.sr = sr;
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trans->transfer.usage = usage;
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trans->transfer.box = *box;
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2010-07-29 19:51:06 +01:00
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trans->transfer.stride = rtex->pitch[sr.level];
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2010-07-28 17:18:19 +01:00
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trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
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2010-08-22 22:13:58 +01:00
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if (rtex->tilled && !rtex->depth) {
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2010-08-22 03:49:22 +01:00
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resource.target = PIPE_TEXTURE_2D;
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resource.format = texture->format;
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resource.width0 = box->width;
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resource.height0 = box->height;
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resource.depth0 = 0;
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resource.last_level = 0;
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resource.nr_samples = 0;
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resource.usage = PIPE_USAGE_DYNAMIC;
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resource.bind = 0;
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resource.flags = 0;
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/* For texture reading, the temporary (detiled) texture is used as
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* a render target when blitting from a tiled texture. */
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if (usage & PIPE_TRANSFER_READ) {
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resource.bind |= PIPE_BIND_RENDER_TARGET;
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}
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/* For texture writing, the temporary texture is used as a sampler
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* when blitting into a tiled texture. */
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if (usage & PIPE_TRANSFER_WRITE) {
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|
|
resource.bind |= PIPE_BIND_SAMPLER_VIEW;
|
|
|
|
}
|
|
|
|
/* Create the temporary texture. */
|
|
|
|
trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
|
|
|
|
if (trans->linear_texture == NULL) {
|
|
|
|
R600_ERR("failed to create temporary texture to hold untiled copy\n");
|
|
|
|
pipe_resource_reference(&trans->transfer.resource, NULL);
|
|
|
|
FREE(trans);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
if (usage & PIPE_TRANSFER_READ) {
|
|
|
|
/* We cannot map a tiled texture directly because the data is
|
|
|
|
* in a different order, therefore we do detiling using a blit. */
|
|
|
|
r600_copy_from_tiled_texture(ctx, trans);
|
|
|
|
/* Always referenced in the blit. */
|
|
|
|
ctx->flush(ctx, 0, NULL);
|
|
|
|
}
|
|
|
|
}
|
2010-07-28 17:18:19 +01:00
|
|
|
return &trans->transfer;
|
|
|
|
}
|
|
|
|
|
|
|
|
void r600_texture_transfer_destroy(struct pipe_context *ctx,
|
2010-08-22 03:49:22 +01:00
|
|
|
struct pipe_transfer *transfer)
|
2010-07-28 17:18:19 +01:00
|
|
|
{
|
2010-08-22 03:49:22 +01:00
|
|
|
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
|
|
|
|
|
|
|
|
if (rtransfer->linear_texture) {
|
|
|
|
pipe_resource_reference(&rtransfer->linear_texture, NULL);
|
|
|
|
}
|
|
|
|
pipe_resource_reference(&transfer->resource, NULL);
|
|
|
|
FREE(transfer);
|
2010-07-28 17:18:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void* r600_texture_transfer_map(struct pipe_context *ctx,
|
|
|
|
struct pipe_transfer* transfer)
|
|
|
|
{
|
|
|
|
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
|
2010-08-22 22:13:58 +01:00
|
|
|
struct radeon_bo *bo;
|
2010-07-28 17:18:19 +01:00
|
|
|
enum pipe_format format = transfer->resource->format;
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
2010-08-22 22:13:58 +01:00
|
|
|
struct r600_resource_texture *rtex;
|
|
|
|
unsigned long offset = 0;
|
2010-07-28 17:18:19 +01:00
|
|
|
char *map;
|
2010-08-22 22:13:58 +01:00
|
|
|
int r;
|
2010-05-10 02:27:58 +01:00
|
|
|
|
2010-08-04 21:28:33 +01:00
|
|
|
r600_flush(ctx, 0, NULL);
|
2010-08-22 03:49:22 +01:00
|
|
|
if (rtransfer->linear_texture) {
|
2010-08-22 22:13:58 +01:00
|
|
|
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
|
2010-08-22 03:49:22 +01:00
|
|
|
} else {
|
2010-08-22 22:13:58 +01:00
|
|
|
rtex = (struct r600_resource_texture*)transfer->resource;
|
|
|
|
if (rtex->depth) {
|
|
|
|
r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
|
|
|
|
if (r) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
r600_flush(ctx, 0, NULL);
|
|
|
|
bo = rtex->uncompressed;
|
|
|
|
} else {
|
|
|
|
bo = ((struct r600_resource *)transfer->resource)->bo;
|
|
|
|
}
|
|
|
|
offset = rtransfer->offset +
|
|
|
|
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
|
|
|
|
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
|
2010-08-22 03:49:22 +01:00
|
|
|
}
|
2010-08-22 22:13:58 +01:00
|
|
|
if (radeon_bo_map(rscreen->rw, bo)) {
|
2010-07-28 17:18:19 +01:00
|
|
|
return NULL;
|
|
|
|
}
|
2010-08-22 22:13:58 +01:00
|
|
|
radeon_bo_wait(rscreen->rw, bo);
|
2010-05-10 02:27:58 +01:00
|
|
|
|
2010-08-22 22:13:58 +01:00
|
|
|
map = bo->data;
|
|
|
|
return map + offset;
|
2010-05-08 21:09:24 +01:00
|
|
|
}
|
|
|
|
|
2010-07-28 17:18:19 +01:00
|
|
|
void r600_texture_transfer_unmap(struct pipe_context *ctx,
|
|
|
|
struct pipe_transfer* transfer)
|
2010-05-08 21:09:24 +01:00
|
|
|
{
|
2010-08-22 03:49:22 +01:00
|
|
|
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
|
2010-07-28 17:18:19 +01:00
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
2010-08-22 22:13:58 +01:00
|
|
|
struct r600_resource_texture *rtex;
|
|
|
|
struct radeon_bo *bo;
|
2010-05-10 02:27:58 +01:00
|
|
|
|
2010-08-22 03:49:22 +01:00
|
|
|
if (rtransfer->linear_texture) {
|
2010-08-22 22:13:58 +01:00
|
|
|
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
|
2010-08-22 03:49:22 +01:00
|
|
|
} else {
|
2010-08-22 22:13:58 +01:00
|
|
|
rtex = (struct r600_resource_texture*)transfer->resource;
|
|
|
|
if (rtex->depth) {
|
|
|
|
bo = rtex->uncompressed;
|
|
|
|
} else {
|
|
|
|
bo = ((struct r600_resource *)transfer->resource)->bo;
|
|
|
|
}
|
2010-08-22 03:49:22 +01:00
|
|
|
}
|
2010-08-22 22:13:58 +01:00
|
|
|
radeon_bo_unmap(rscreen->rw, bo);
|
2010-05-08 21:09:24 +01:00
|
|
|
}
|
|
|
|
|
2010-05-10 02:27:58 +01:00
|
|
|
struct u_resource_vtbl r600_texture_vtbl =
|
|
|
|
{
|
2010-07-28 17:18:19 +01:00
|
|
|
u_default_resource_get_handle, /* get_handle */
|
2010-05-10 02:27:58 +01:00
|
|
|
r600_texture_destroy, /* resource_destroy */
|
|
|
|
r600_texture_is_referenced, /* is_resource_referenced */
|
|
|
|
r600_texture_get_transfer, /* get_transfer */
|
|
|
|
r600_texture_transfer_destroy, /* transfer_destroy */
|
|
|
|
r600_texture_transfer_map, /* transfer_map */
|
|
|
|
u_default_transfer_flush_region,/* transfer_flush_region */
|
|
|
|
r600_texture_transfer_unmap, /* transfer_unmap */
|
|
|
|
u_default_transfer_inline_write /* transfer_inline_write */
|
|
|
|
};
|
|
|
|
|
2010-05-08 21:09:24 +01:00
|
|
|
void r600_init_screen_texture_functions(struct pipe_screen *screen)
|
|
|
|
{
|
|
|
|
screen->get_tex_surface = r600_get_tex_surface;
|
|
|
|
screen->tex_surface_destroy = r600_tex_surface_destroy;
|
|
|
|
}
|
2010-08-12 07:06:40 +01:00
|
|
|
|
|
|
|
static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
|
2010-08-22 03:49:22 +01:00
|
|
|
const unsigned char *swizzle_view)
|
2010-08-12 07:06:40 +01:00
|
|
|
{
|
2010-08-22 03:49:22 +01:00
|
|
|
unsigned i;
|
|
|
|
unsigned char swizzle[4];
|
|
|
|
unsigned result = 0;
|
|
|
|
const uint32_t swizzle_shift[4] = {
|
|
|
|
16, 19, 22, 25,
|
|
|
|
};
|
|
|
|
const uint32_t swizzle_bit[4] = {
|
|
|
|
0, 1, 2, 3,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (swizzle_view) {
|
|
|
|
/* Combine two sets of swizzles. */
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
|
|
|
|
swizzle_format[swizzle_view[i]] : swizzle_view[i];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
memcpy(swizzle, swizzle_format, 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get swizzle. */
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
switch (swizzle[i]) {
|
|
|
|
case UTIL_FORMAT_SWIZZLE_Y:
|
|
|
|
result |= swizzle_bit[1] << swizzle_shift[i];
|
|
|
|
break;
|
|
|
|
case UTIL_FORMAT_SWIZZLE_Z:
|
|
|
|
result |= swizzle_bit[2] << swizzle_shift[i];
|
|
|
|
break;
|
|
|
|
case UTIL_FORMAT_SWIZZLE_W:
|
|
|
|
result |= swizzle_bit[3] << swizzle_shift[i];
|
|
|
|
break;
|
|
|
|
case UTIL_FORMAT_SWIZZLE_0:
|
|
|
|
result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
|
|
|
|
break;
|
|
|
|
case UTIL_FORMAT_SWIZZLE_1:
|
|
|
|
result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
|
|
|
|
break;
|
|
|
|
default: /* UTIL_FORMAT_SWIZZLE_X */
|
|
|
|
result |= swizzle_bit[0] << swizzle_shift[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return result;
|
2010-08-12 07:06:40 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* texture format translate */
|
|
|
|
uint32_t r600_translate_texformat(enum pipe_format format,
|
|
|
|
const unsigned char *swizzle_view,
|
|
|
|
uint32_t *word4_p, uint32_t *yuv_format_p)
|
|
|
|
{
|
|
|
|
uint32_t result = 0, word4 = 0, yuv_format = 0;
|
|
|
|
const struct util_format_description *desc;
|
|
|
|
boolean uniform = TRUE;
|
|
|
|
int i;
|
|
|
|
const uint32_t sign_bit[4] = {
|
|
|
|
S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
|
|
|
|
S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
|
|
|
|
S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
|
|
|
|
S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
|
|
|
|
};
|
|
|
|
desc = util_format_description(format);
|
|
|
|
|
2010-09-02 06:51:23 +01:00
|
|
|
word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
|
|
|
|
|
2010-08-12 07:06:40 +01:00
|
|
|
/* Colorspace (return non-RGB formats directly). */
|
|
|
|
switch (desc->colorspace) {
|
|
|
|
/* Depth stencil formats */
|
|
|
|
case UTIL_FORMAT_COLORSPACE_ZS:
|
|
|
|
switch (format) {
|
|
|
|
case PIPE_FORMAT_Z16_UNORM:
|
2010-08-22 03:49:22 +01:00
|
|
|
result = V_0280A0_COLOR_16;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case PIPE_FORMAT_Z24X8_UNORM:
|
2010-08-22 03:49:22 +01:00
|
|
|
result = V_0280A0_COLOR_8_24;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
|
2010-08-22 03:49:22 +01:00
|
|
|
result = V_0280A0_COLOR_8_24;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
default:
|
|
|
|
goto out_unknown;
|
|
|
|
}
|
|
|
|
|
|
|
|
case UTIL_FORMAT_COLORSPACE_YUV:
|
|
|
|
yuv_format |= (1 << 30);
|
|
|
|
switch (format) {
|
|
|
|
case PIPE_FORMAT_UYVY:
|
|
|
|
case PIPE_FORMAT_YUYV:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
goto out_unknown; /* TODO */
|
|
|
|
|
|
|
|
case UTIL_FORMAT_COLORSPACE_SRGB:
|
|
|
|
word4 |= S_038010_FORCE_DEGAMMA(1);
|
|
|
|
if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
|
|
|
|
goto out_unknown; /* fails for some reason - TODO */
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* S3TC formats. TODO */
|
|
|
|
if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
|
|
|
|
goto out_unknown;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < desc->nr_channels; i++) {
|
|
|
|
if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
|
|
|
|
word4 |= sign_bit[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* R8G8Bx_SNORM - TODO CxV8U8 */
|
|
|
|
|
|
|
|
/* RGTC - TODO */
|
|
|
|
|
|
|
|
/* See whether the components are of the same size. */
|
|
|
|
for (i = 1; i < desc->nr_channels; i++) {
|
|
|
|
uniform = uniform && desc->channel[0].size == desc->channel[i].size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Non-uniform formats. */
|
|
|
|
if (!uniform) {
|
|
|
|
switch(desc->nr_channels) {
|
|
|
|
case 3:
|
|
|
|
if (desc->channel[0].size == 5 &&
|
|
|
|
desc->channel[1].size == 6 &&
|
|
|
|
desc->channel[2].size == 5) {
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_5_6_5;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
case 4:
|
|
|
|
if (desc->channel[0].size == 5 &&
|
|
|
|
desc->channel[1].size == 5 &&
|
|
|
|
desc->channel[2].size == 5 &&
|
|
|
|
desc->channel[3].size == 1) {
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_1_5_5_5;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
if (desc->channel[0].size == 10 &&
|
|
|
|
desc->channel[1].size == 10 &&
|
|
|
|
desc->channel[2].size == 10 &&
|
|
|
|
desc->channel[3].size == 2) {
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_10_10_10_2;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* uniform formats */
|
|
|
|
switch (desc->channel[0].type) {
|
|
|
|
case UTIL_FORMAT_TYPE_UNSIGNED:
|
|
|
|
case UTIL_FORMAT_TYPE_SIGNED:
|
|
|
|
if (!desc->channel[0].normalized &&
|
|
|
|
desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
|
|
|
|
goto out_unknown;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (desc->channel[0].size) {
|
|
|
|
case 4:
|
|
|
|
switch (desc->nr_channels) {
|
|
|
|
case 2:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_4_4;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 4:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_4_4_4_4;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
case 8:
|
|
|
|
switch (desc->nr_channels) {
|
|
|
|
case 1:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_8;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 2:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_8_8;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 4:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_8_8_8_8;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
case 16:
|
|
|
|
switch (desc->nr_channels) {
|
|
|
|
case 1:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 2:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16_16;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 4:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16_16_16_16;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
|
|
|
|
case UTIL_FORMAT_TYPE_FLOAT:
|
|
|
|
switch (desc->channel[0].size) {
|
|
|
|
case 16:
|
|
|
|
switch (desc->nr_channels) {
|
|
|
|
case 1:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 2:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16_16_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 4:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_16_16_16_16_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
goto out_unknown;
|
|
|
|
case 32:
|
|
|
|
switch (desc->nr_channels) {
|
|
|
|
case 1:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_32_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 2:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_32_32_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
case 4:
|
2010-09-03 05:38:41 +01:00
|
|
|
result = V_0280A0_COLOR_32_32_32_32_FLOAT;
|
2010-08-12 07:06:40 +01:00
|
|
|
goto out_word4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
out_word4:
|
|
|
|
if (word4_p)
|
|
|
|
*word4_p = word4;
|
|
|
|
if (yuv_format_p)
|
|
|
|
*yuv_format_p = yuv_format;
|
|
|
|
return result;
|
|
|
|
out_unknown:
|
2010-09-01 23:04:38 +01:00
|
|
|
// R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
|
2010-08-12 07:06:40 +01:00
|
|
|
return ~0;
|
|
|
|
}
|
2010-08-22 19:22:00 +01:00
|
|
|
|
|
|
|
int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
|
|
|
|
{
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (!rtexture->depth) {
|
|
|
|
/* This shouldn't happen maybe print a warning */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (rtexture->uncompressed && !rtexture->dirty) {
|
|
|
|
/* Uncompressed bo already in good state */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* allocate uncompressed texture */
|
|
|
|
if (rtexture->uncompressed == NULL) {
|
|
|
|
rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
|
|
|
|
if (rtexture->uncompressed == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* render a rectangle covering whole buffer to uncompress depth */
|
|
|
|
r = r600_blit_uncompress_depth(ctx, rtexture, level);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
rtexture->dirty = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
static void r600_texture_state_scissor(struct r600_screen *rscreen,
|
2010-08-22 19:22:00 +01:00
|
|
|
struct r600_resource_texture *rtexture,
|
|
|
|
unsigned level)
|
|
|
|
{
|
2010-08-30 22:56:59 +01:00
|
|
|
struct radeon_state *rstate = &rtexture->scissor[level];
|
2010-08-22 19:22:00 +01:00
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
|
2010-08-22 19:22:00 +01:00
|
|
|
/* set states (most default value are 0 and struct already
|
|
|
|
* initialized to 0, thus avoid resetting them)
|
|
|
|
*/
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
|
|
|
|
rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_pm4(rstate);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
|
2010-08-22 19:22:00 +01:00
|
|
|
{
|
|
|
|
struct radeon_state *rstate;
|
|
|
|
struct r600_resource *rbuffer;
|
|
|
|
unsigned pitch, slice;
|
|
|
|
unsigned color_info;
|
|
|
|
unsigned format, swap, ntype;
|
|
|
|
const struct util_format_description *desc;
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
rstate = &rtexture->cb[cb][level];
|
|
|
|
radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
|
2010-08-22 19:22:00 +01:00
|
|
|
rbuffer = &rtexture->resource;
|
|
|
|
|
|
|
|
/* set states (most default value are 0 and struct already
|
|
|
|
* initialized to 0, thus avoid resetting them)
|
|
|
|
*/
|
|
|
|
pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
|
|
|
|
slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
|
|
|
|
ntype = 0;
|
|
|
|
desc = util_format_description(rbuffer->base.b.format);
|
|
|
|
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
|
|
|
|
ntype = V_0280A0_NUMBER_SRGB;
|
|
|
|
format = r600_translate_colorformat(rtexture->resource.base.b.format);
|
|
|
|
swap = r600_translate_colorswap(rtexture->resource.base.b.format);
|
|
|
|
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
|
|
|
|
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
|
|
|
|
rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
|
|
|
|
rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
|
|
|
|
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->nbo = 3;
|
2010-08-22 22:13:58 +01:00
|
|
|
color_info = 0;
|
2010-08-22 19:22:00 +01:00
|
|
|
} else {
|
|
|
|
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
|
|
|
|
rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
|
|
|
|
rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
|
|
|
|
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->nbo = 3;
|
2010-08-22 22:13:58 +01:00
|
|
|
color_info = S_0280A0_SOURCE_FORMAT(1);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
2010-08-22 22:13:58 +01:00
|
|
|
color_info |= S_0280A0_FORMAT(format) |
|
|
|
|
S_0280A0_COMP_SWAP(swap) |
|
|
|
|
S_0280A0_BLEND_CLAMP(1) |
|
|
|
|
S_0280A0_NUMBER_TYPE(ntype);
|
2010-08-27 06:45:58 +01:00
|
|
|
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
|
|
|
|
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
|
|
|
|
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
|
2010-08-22 19:22:00 +01:00
|
|
|
S_028060_SLICE_TILE_MAX(slice);
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_pm4(rstate);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
|
2010-08-22 19:22:00 +01:00
|
|
|
{
|
2010-08-30 22:56:59 +01:00
|
|
|
struct radeon_state *rstate = &rtexture->db[level];
|
2010-08-22 19:22:00 +01:00
|
|
|
struct r600_resource *rbuffer;
|
|
|
|
unsigned pitch, slice, format;
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
|
2010-08-22 19:22:00 +01:00
|
|
|
rbuffer = &rtexture->resource;
|
2010-09-01 18:04:42 +01:00
|
|
|
rtexture->tilled = 1;
|
|
|
|
rtexture->array_mode = 2;
|
|
|
|
rtexture->tile_type = 1;
|
|
|
|
rtexture->depth = 1;
|
2010-08-22 19:22:00 +01:00
|
|
|
|
|
|
|
/* set states (most default value are 0 and struct already
|
|
|
|
* initialized to 0, thus avoid resetting them)
|
|
|
|
*/
|
|
|
|
pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
|
|
|
|
slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
|
|
|
|
format = r600_translate_dbformat(rbuffer->base.b.format);
|
|
|
|
rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
|
|
|
|
rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
|
|
|
|
S_028010_FORMAT(format);
|
|
|
|
rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
|
|
|
|
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
|
|
|
|
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
|
|
|
|
S_028000_SLICE_TILE_MAX(slice);
|
|
|
|
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
|
|
|
|
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
|
|
|
|
rstate->nbo = 1;
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_pm4(rstate);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
|
|
|
|
{
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
if (!rtexture->scissor[level].cpm4) {
|
|
|
|
r600_texture_state_scissor(rscreen, rtexture, level);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
|
2010-08-22 22:13:58 +01:00
|
|
|
{
|
2010-08-30 22:56:59 +01:00
|
|
|
struct radeon_state *rstate = &rtexture->viewport[level];
|
2010-08-22 22:13:58 +01:00
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
|
2010-08-22 22:13:58 +01:00
|
|
|
|
|
|
|
/* set states (most default value are 0 and struct already
|
|
|
|
* initialized to 0, thus avoid resetting them)
|
|
|
|
*/
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
|
|
|
|
rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
|
|
|
|
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
radeon_state_pm4(rstate);
|
2010-08-22 22:13:58 +01:00
|
|
|
}
|
|
|
|
|
2010-09-01 18:04:42 +01:00
|
|
|
int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
|
2010-08-22 19:22:00 +01:00
|
|
|
{
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
if (!rtexture->cb[cb][level].cpm4) {
|
|
|
|
r600_texture_state_cb(rscreen, rtexture, cb, level);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
|
|
|
|
{
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
if (!rtexture->db[level].cpm4) {
|
|
|
|
r600_texture_state_db(rscreen, rtexture, level);
|
2010-08-22 19:22:00 +01:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2010-08-22 22:13:58 +01:00
|
|
|
|
|
|
|
int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
|
|
|
|
{
|
|
|
|
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
|
|
|
|
2010-08-30 22:56:59 +01:00
|
|
|
if (!rtexture->viewport[level].cpm4) {
|
|
|
|
r600_texture_state_viewport(rscreen, rtexture, level);
|
2010-08-22 22:13:58 +01:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|